Method for forming semiconductor

Abstract

The invention provides a method for forming a semiconductor, which comprises the steps of providing a semiconductor; forming a tunneling oxide layer on the semiconductor; etching the tunneling oxide layer and the substrate to form a shallow trench isolation structure; sequentially forming a floating gate layer and a mask layer on the tunneling oxide layer and the shallow trench isolation structure; etching the mask layer and the floating gate layer to form a trench, a patterned floating gate layer and a patterned mask layer; filling the trench with oxide by taking the patterned mask layer as amask; removing the patterned mask layer; performing wet etching on the patterned floating gate layer to enable corners of the patterned floating gate layer to be rounded; carrying out dry etching onpart of the oxide in the trench; and performing wet etching on the remaining part of the oxide in the trench. According to the method provided by the invention for forming the semiconductor, a methodof carrying out wet etching, drying etching and wet etching is adopted after the right-angled columnar patterned floating gate layer is formed, so that the etching amount can be balanced, the deviation of the etching amount can be reduced, and finally, the programming and reading of a semiconductor device can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor. Background technique [0002] At present, in the 19NAND project, the process of etching the ST I oxide layer on the side of the floating gate is a wet etching plus dry etching process, which realizes the smoothness of the top of the floating gate, consumes part of the side wall of the floating gate, and increases the space. The bottom of the U-shaped groove is smooth to prevent tip discharge. The wet etching plus dry etching process has the problem that the etching accuracy is greatly affected by the dimensional consistency of the active area, which directly affects the control of key etching accuracy parameters. The specific performance is: small area etching is relatively Slower, and faster for large areas. The present invention deeply analyzes the root cause of the fluctuation of the etching precision, which is that the dry etchin...

AI Technical Summary

Problems solved by technology

The wet etching plus dry etching process has the problem that the etching accuracy is greatly affected by the dimensional consistency of the active area, which directly affects the control of key etching accuracy parameters. The specific performance is: small area etching is relatively slower, and faster for large areas

The present invention deeply analyzes the root cause of the fluctuation of the etching precision, which is that the dry etching process is very sensitive to the etched area. During dry etching, the etching rate of small areas is relatively slow, while that of large areas is relatively fast. In the end, the deviation of etching accuracy far exceeds the range of + / -20A, resulting in abnormal reading and writing of the array, crosstalk and other problems

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