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Scanning test compression optimization method

A technology of scanning test and optimization method, applied in the field of image sensor, can solve problems such as increasing test difficulty, and achieve the effect of improving test efficiency and yield, low loss of fault coverage, and high test compression efficiency

Inactive Publication Date: 2020-01-14
TIANJIN UNIV
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Problems solved by technology

[0002] DFT (Design for Test) technology is an effective way to solve the test of VLSI. With the expansion of the chip scale, the test data volume and test time of the chip will increase accordingly. ATE (Automatic Test Equipment) needs to provide more Memory and test data transmission channels to meet the test requirements, increasing the difficulty of testing

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Embodiment Construction

[0021] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0022] The scan test of the chip is divided into three processes of test initialization, shift and capture. Each test vector will complete its own shift and capture. The shift occupies most of the time of the scan test. Therefore, only the scan shift is considered. Under data and cycle conditions, the volume of scan test data V test and test time T test They can be calculated by the following formulas respectively:

[0023] V test =IOs*Patterns*Cycles (1)

[0024]

[0025] In the formula: IOs is the number of scanning test ports, Patterns is the number of test vectors, Cycles is the number of shift cycles of test vectors, F shift In order to test the clock frequency, the value...

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Abstract

The invention discloses a scanning test compression optimization method. The method comprises the following steps: firstly, measuring the loss of fault coverage by adopting a method for analyzing a compression rate; improving the compression ratio through a method of fixing a scanning channel within the range meeting the coverage requirements, properly reducing the length of each scanning chain and increasing the number of the scanning chains, and analyzing test compression results of test vector and test time and the like; increasing the number of the scanning channels by adopting a fixed compression ratio mode, increasing the number of scanning chains under the condition that the degree of parallelism is not changed, and meanwhile, reducing the length of the scanning chains; analyzing test compression results of test vectors and test time and the like; and finally, obtaining an optimal length range of the scanning chains and the optimal number of the scanning chains by integrating the two aspects. According to the invention, a more optimized test compression scheme can be provided, and the cost of the chip in the test link is reduced.

Description

technical field [0001] The invention relates to the technical field of image sensors, in particular to an optimization method for scanning test compression. Background technique [0002] DFT (Design for Test) technology is an effective way to solve the test of VLSI. With the expansion of the chip scale, the test data volume and test time of the chip will increase accordingly. ATE (Automatic Test Equipment) needs to provide more Memory and test data transmission channels are used to meet test requirements, which increases the difficulty of testing. The embedded test compression method is to add compression logic to the scanning circuit to realize the decompression of the test stimulus and the compression of the test response, thereby reducing the number of test data and test channels, and adopting a reasonable method to optimize the design of the test compression circuit can maximize the Reduce test vector volume and test time. [0003] The compression of the scan test is m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185G01R31/317G01R31/28
CPCG01R31/2851G01R31/31718G01R31/318533
Inventor 赵毅强李松林元琦甄帅
Owner TIANJIN UNIV
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