Preparation method of heterojunction battery

Abstract

The invention discloses a preparation method of a heterojunction battery. The heterojunction battery comprises a gate electrode, a transparent conductive layer, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, a monocrystalline silicon substrate, an intrinsic amorphous silicon layer, a p-type amorphous silicon layer, a transparent conductive layer and a gate electrode whichare sequentially arranged, and the preparation method comprises the following steps of performing a coating process and a wafer turning process of the intrinsic amorphous silicon layer on one end surface of the monocrystalline silicon substrate; performing a coating process of the intrinsic amorphous silicon layer on the other end surface opposite to the end surface of the monocrystalline siliconsubstrate; performing a coating process and a wafer turning process of the n-type amorphous silicon layer; and performing a coating process of the p-type amorphous silicon layer. The preparation method can reduce the pollution of the doped n-type or p-type material to the surface of a silicon wafer of which the other surface is not plated with the intrinsic amorphous silicon layer, and moreover,the process temperature of each film layer during film coating can be better matched, so that the performance of the heterojunction battery is improved.

Description

technical field [0001] The invention relates to the technical field of battery manufacturing, in particular to a method for preparing a heterojunction battery. Background technique [0002] The heterojunction cell includes a single crystal silicon substrate, intrinsic amorphous silicon layers respectively disposed on opposite ends of the single crystal silicon substrate, p-type amorphous silicon layers respectively disposed on the intrinsic amorphous silicon layers on both sides, and An n-type amorphous silicon layer, a transparent conductive layer respectively arranged on the p-type amorphous silicon layer and an n-type amorphous silicon layer, and gate electrodes respectively arranged on both sides of the transparent conductive layer. [0003] In the prior art, in order to reduce the possible damage caused by the turning over of the heterojunction cell during the preparation of the heterojunction cell, the cell is generally turned upside down after completing all the thin ...

AI Technical Summary

Problems solved by technology

However, the doped n or p-type material in this preparation method will inevitably contaminate the surface of the silicon wafer that is not coated with an intrinsic amorphous silicon layer on the other side, thereby affecting the performance of the heterojunction cell.