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Semiconductor memory and forming method thereof

A memory and semiconductor technology, applied in the direction of semiconductor devices, electric solid devices, electrical components, etc., can solve the problem of excessive parasitic capacitance of memory, achieve the effect of improving capacitive coupling, alleviating parasitic capacitance, and avoiding mutual interference

Pending Publication Date: 2020-03-13
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The object of the present invention is to provide a semiconductor memory to solve the problem of excessive parasitic capacitance of the existing semiconductor memory

Method used

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  • Semiconductor memory and forming method thereof
  • Semiconductor memory and forming method thereof
  • Semiconductor memory and forming method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0076] figure 1 is a top view of the semiconductor memory in Embodiment 1 of the present invention, figure 2 It is a partially enlarged view of the active region of the semiconductor memory in Embodiment 1 of the present invention, Figure 3a , Figure 3b and Figure 3c for figure 1 Shown is a schematic cross-sectional view of the semiconductor memory in Embodiment 1 of the present invention along the aa', bb' and cc' directions.

[0077] combine figure 1 and figure 2 As shown, the semiconductor memory in this embodiment includes a substrate 100 .

[0078] Specifically, a trench isolation structure 110 is formed in the substrate 100 and defines at least one active area AA. It can be considered that the trench isolation structure 110 is formed in the substrate 100 and surrounds the periphery of the active area AA, so as to isolate a plurality of active areas AA from each other. Preferably, the trench isolation structure 110 is embedded in the substrate 100 and further...

Embodiment 2

[0109] This embodiment provides a method for forming a semiconductor memory, Figure 4It is a schematic flow chart of the method for forming a semiconductor memory in Embodiment 2 of the present invention, refer to Figure 4 As shown, the forming method of the semiconductor memory includes:

[0110] In step S100, a substrate is provided, in which a trench isolation structure is formed and at least one active region is defined, and the active region includes a first extension region extending along a first direction and a first extension region extending along a first direction. The second extension area extending in two directions, the ends of the first extension area and the second extension area are connected to each other to form a connection area, wherein the part of the first extension area away from the connection area is used to form a first doped region, and a second doped region is formed in a part of the second extension region away from the connecting region;

[0...

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Abstract

The invention provides a semiconductor memory and a forming method thereof. According to the semiconductor memory, a second doped region is formed in the end part of an active region of the semiconductor memory, so that the bit lines can be connected with the second doped region from the end part of the active region, the bit lines can be buried in the substrate, and the adjacent bit lines are isolated by utilizing a trench isolation structure, and accordingly the phenomenon of capacitive coupling between the adjacent bit lines can be improved. Meanwhile, the bit lines are buried in the substrate, so that the parasitic capacitance between the bit lines and the word lines formed on the substrate can be correspondingly relieved, and the device performance of the semiconductor memory is further improved. In addition, the word lines in a storage array area and the grid conducting layers of the peripheral transistors can be prepared simultaneously, and the technological process is saved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits and semiconductors, in particular to a semiconductor memory and a forming method thereof. Background technique [0002] As the semiconductor industry enters a new era of high-performance and multi-functional integrated circuits, the density of semiconductor components in integrated circuits will increase, so that the spacing between semiconductor components will be reduced, which will further increase the use of semiconductor components. The distance between the conducting parts for conducting electrical signals is also correspondingly reduced, which will directly lead to the increase of the parasitic capacitance generated between any two adjacent conducting parts. In particular, as the size of semiconductors continues to shrink, the parasitic capacitance generated between adjacent conductive parts and the interference caused by the parasitic capacitance become more and more obvious. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/105
CPCH01L27/105
Inventor 朱梦娜
Owner CHANGXIN MEMORY TECH INC