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Bit line screening method, device, storage device and storage medium

A screening method and bit line technology, applied in static memory, instruments, etc., can solve problems such as difficult detection and achieve accurate detection effect

Active Publication Date: 2022-05-27
GIGADEVICE SEMICON (BEIJING) INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of implementing the present invention, the inventor found that the prior art has the following defects: it is difficult to detect potential failed bit lines that will only appear after a period of use

Method used

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  • Bit line screening method, device, storage device and storage medium
  • Bit line screening method, device, storage device and storage medium
  • Bit line screening method, device, storage device and storage medium

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0043] figure 1 This is a flowchart of a bit line screening method provided in Embodiment 1 of the present invention. The method in this embodiment can be performed by a bit line screening device, which can be implemented in hardware and / or software, and can generally be integrated in the storage device. The method of this embodiment specifically includes:

[0044] S101, respectively applying a first detection voltage and a second detection voltage for a set time to all the bit lines in each of the to-be-detected regions that are independent of each other by applying the same voltage at intervals, and simultaneously apply the same voltage to all the bit lines in each of the to-be-detected regions respectively. All word lines are applied with cut-off voltages for a set time, wherein the voltage difference between the first detection voltage and the second detection voltage is greater than the set voltage difference.

[0045] In this embodiment, the to-be-detected area may spe...

Embodiment 2

[0059] figure 2 This is a flowchart of a bit line screening method provided by the second embodiment of the present invention. This embodiment is optimized on the basis of the above-mentioned embodiment. In this embodiment, a specific source voltage application method is provided, and it is determined whether to discard the to-be-detected area according to the number of defective bit lines included, and the number of defective bit lines is increased. Embodiments of substitution of lines and substitution steps of discarding areas to be inspected.

[0060] Correspondingly, the method of this embodiment specifically includes:

[0061] S201, respectively applying a first detection voltage and a second detection voltage for a set time to all the bit lines in each of the regions to be detected that are independent of each other by applying the same voltage at intervals, and simultaneously apply the same voltage to all the bit lines in each region to be detected that are independen...

Embodiment 3

[0082] image 3 It is a structural diagram of a bit line screening device provided in Embodiment 3 of the present invention. like image 3 As shown, the device includes: a voltage application module 301, a programming module 302, a verification module 303 and a failed bit line determination module 304, wherein:

[0083] The voltage applying module 301 is used to respectively apply the first detection voltage and the second detection voltage for a set time to all the bit lines in each of the independent regions to be detected by applying the same voltage at intervals. All word lines in the to-be-detected area are applied with a cut-off voltage for a set time, wherein the voltage difference between the first detection voltage and the second detection voltage is greater than the set voltage difference;

[0084] The programming module 302 is used to perform a verification programming operation on each to-be-detected area respectively, so that the data stored by any two adjacent ...

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Abstract

The embodiment of the invention discloses a bit line screening method, device, storage device and storage medium. The method includes: applying the first detection voltage and the second detection voltage for a set time to all bit lines in each area to be detected independently by applying the same voltage at intervals, and applying the first detection voltage and the second detection voltage to all bit lines in each area to be detected Apply a cut-off voltage for a set time to the line; perform a verification programming operation on each area to be tested, so that the data stored in any two adjacent memory cells in each area to be tested is different; verify all data stored in each area to be tested Whether the stored data of the memory cell matches the verification programming operation; and the bit line corresponding to the memory cell whose storage data does not match the verification programming operation is determined as a failed bit line. The technical solution of the embodiment of the present invention solves the technical defect that the existing failure bit line detection method is difficult to detect potential failure bit lines, and realizes rapid and accurate detection of all failure bit lines at one time.

Description

technical field [0001] Embodiments of the present invention relate to the technical field of storage device detection, and in particular, to a bit line screening method, device, storage device, and storage medium. Background technique [0002] For mass production of semiconductor devices, failure analysis of semiconductor devices after design and manufacture is an important means to increase yield and improve reliability and stability of process technology. [0003] For semiconductor memory devices, the short circuit between the bit lines is a common failure situation. The short circuit of the bit line will make all the memory cells on the two bit lines lose their function, reducing the storage capacity of the memory chip. Bitline failure analysis of memory devices is very important. In the prior art, specifically, whether the voltage between each two bit lines exceeds a threshold value is measured by an electrical test (chip probing test), so as to find out the position of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/50G11C29/00
CPCG11C29/50G11C29/006G11C29/838G11C2029/5004
Inventor 张赛苏如伟冯骏
Owner GIGADEVICE SEMICON (BEIJING) INC