Open-loop metastable state detection and correction method

A metastable, test fixture technology for radar applications

Active Publication Date: 2020-04-03
CNGC INST NO 206 OF CHINA ARMS IND GRP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In order to solve the metastable problem between the local logic clock and PRF signal of frequency synthesis, make the initial phase of complex waveform signal stable

Method used

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  • Open-loop metastable state detection and correction method
  • Open-loop metastable state detection and correction method
  • Open-loop metastable state detection and correction method

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Embodiment Construction

[0022] Now in conjunction with embodiment, accompanying drawing, the present invention will be further described:

[0023] The present invention is made up of 2 parts: frequency synthesis, test tooling (simulation signal place produces timing);

[0024] 1) Frequency synthesis generally includes crystal oscillator, control unit, frequency synthesis unit (local oscillator signal, complex waveform signal, coherent clock signal, etc.);

[0025] 2) The frequency synthesizer outputs the coherent clock signal (generally the sampling clock of the signal office) to the test tool (the frequency synthesizer does not need the test tool for actual work, and the test tool is only for simulating some functions of the signal office for experimental verification);

[0026] 3) The test tool generates a PRF signal based on the coherent clock signal and outputs it to the frequency synthesizer; the frequency synthesizer uses the PRF signal as the output timing of the complex waveform signal;

[0...

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Abstract

The invention relates to an open-loop metastable state detection and correction method, and the method comprises the steps of enabling a frequency synthesizer to output a coherent clock signal to a testing tool, enabling the testing tool to generate a PRF signal with the coherent clock signal as the reference, and outputting the PRF signal to the frequency synthesizer; enabling the frequency synthesizer to take the PRF signal as the output timing of a complex waveform signal; and enabling the frequency synthesizer to adopt the metastable state detection logic to judge the edge-edge (rising edge) relationship between a local logic clock and the PRF. The frequency synthesizer can always stably acquire the PRF signal by switching the clock, the edge-collection-edge is avoided, and the problemof metastable state is solved.

Description

technical field [0001] The invention relates to an open-loop detection and correction method for a metastable state, which belongs to the technical field of radar and is applied in a radar system. Background technique [0002] In the radar system, the frequency synthesizer (hereinafter referred to as "frequency synthesizer") usually outputs a coherent clock signal to the signal processor (hereinafter referred to as "information office"), and the information office generates radar system timing signals based on the clock. Among them, the output The PRF (pulse repetition frequency, Pulse Repeat Frequency) signal to the frequency synthesis is used as the output timing of the frequency synthesis complex waveform signal, and the frequency synthesis uses the local logic clock (same source as the PRF signal) to sample the PRF signal to determine the output start of the complex waveform signal . Due to the time delay of the PRF signal transmission link, device temperature drift, an...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01S7/40
CPCG01S7/4004
Inventor 朱康生余铁军王栋由法宝郝金华王瑞斌于萌
Owner CNGC INST NO 206 OF CHINA ARMS IND GRP
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