Manufacturing method of non-volatile memory device

Abstract

Provided herein is a method of fabricating a nonvolatile memory device. This method includes the following steps. A plurality of isolation structures are formed in the substrate, and recessed regions are formed between adjacent isolation structures. A conductive layer and a sacrificial layer are conformally formed on the isolation structure and the substrate. The sacrificial layer in the recessed region defines the recessed portion. A first chemical mechanical polishing process is performed to partially remove the sacrificial layer and expose the conductive layer over the isolation structure. A second chemical mechanical polishing process is performed to partially remove the conductive layer and expose the top surface of the isolation structure. A third chemical mechanical polishing process is performed to completely remove the sacrificial layer. After the third chemical mechanical polishing process, the top surface of the conductive layer is flush with the top surface of the isolation structure. Through the method provided by the embodiments of the present invention, the yield and reliability of the non-volatile memory device can be improved, and the mask and developing process can be reduced, thereby providing a simpler process and reducing the time and cost required for production.

Description

technical field [0001] The present invention relates to a method of fabricating a non-volatile memory device, and more particularly, to a method of fabricating a non-volatile memory device including a chemical mechanical polishing process. Background technique [0002] Among non-volatile memories, flash memory has gradually become the mainstream technology of non-volatile memory due to its low cost. When manufacturing flash memory, a chemical mechanical polishing (CMP) process is often used for planarization. For example, the step of forming the floating gate and / or the control gate includes planarizing the conductive material by a CMP process. However, due to the difference in size (or pitch) of these floating gates (or control gates), the floating gates (or control gates) are prone to defects due to the CMP process. More specifically, for conductive materials with larger areas (eg, areas greater than 0.5 μm*0.5 μm), the grinding rate of the central region will generally ...

AI Technical Summary

Problems solved by technology

In this way, the complexity and difficulty of the patterning process will be greatly increased, and the time and cost of production will be increased

[0004] However, in the known technology, when the conductive material has a relatively high pattern complexity, the mask layer usually only covers a large area of ​​the conductive material, and other conductive materials not covered by the mask layer may still occur. dishing

As a result, it will be difficult to improve the yield and reliability of memory devices

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