Process method of SGT device

Abstract

The invention discloses a process method of an SGT device. The method comprises the process steps of: 1, forming a trench type gate on a heavily doped semiconductor substrate, namely, forming a trenchon the substrate, then depositing a dielectric layer and a liner oxide layer, and then depositing polycrystalline silicon and etching back to form source polycrystalline silicon; 2, forming a thermaloxidation layer again; 3, depositing an oxide layer again by adopting an HDPCVD method; 4, removing the liner oxide layer at the upper part of the trench; and 5, depositing polycrystalline silicon and performing back etching to complete the manufacturing of the polycrystalline silicon gate at the upper part of the trench. According to the method, an HDPCVD process is added after the conventionalthermal oxide layer deposition process, so that the upper surface of the thermal oxide layer is flatter, the transition of a corner region of the trench is smoother, the defects of recesses on two sides, sharp corners and the like are avoided, and the situation of electric leakage between the polycrystalline silicon gate and a shielding electrode is not easily caused.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a process method of an SGT device. Background technique [0002] In the field of medium and low voltage devices with a withstand voltage above 60V, Shield Gate Trench (SGT) devices are widely used because of their low specific on-resistance and low gate-drain coupling capacitance. The gate structure of SGT devices includes shielded polysilicon and polysilicon gate. Shielded polysilicon is usually also called source polysilicon, which are all formed in the trench. According to the different settings of shielded polysilicon and polysilicon gate in the trench, it is usually divided into upper and lower structures and left and right structures. . In the upper and lower structure, the shielding polysilicon is located at the bottom of the trench, the polysilicon gate is located at the top of the trench, and the polysilicon gate and the shielding polysilicon are in a v...

AI Technical Summary

Problems solved by technology

SGT devices whose operating voltage is above 60V have a thick pad oxide layer, and after removing the pad oxide layer, both sides of the thermal oxide layer are depressed, such as Figure 2-4 As shown, it also causes the oxide layer here to be thinner, causing the leakage between the gate and the source to be too large

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