Static random access memory based on back gate structure of FDSOI device

Abstract

The invention discloses a static random access memory (SRAM) based on a back gate structure of a FDSOI device, all transistors on the novel static random access memory are FDSOI devices, and back gates of the devices are connected with a word line WL. When the SRAM performs read-write operation, the word line is at a high level, so that the threshold voltage of the PMOS is increased, and the threshold voltage of the NMOS is reduced, thereby enhancing the write-in capability of the SRAM and improving the read current; in the maintaining state, the word line WL is at a low level, and the threshold voltage of the device on the SRAM is not different from the threshold voltage of the device on the traditional FDSOI SRAM, so that the static power consumption is not changed.

Description

technical field [0001] The invention belongs to the technical field of CMOS very large integrated circuits (VLSI), and in particular relates to a static random access memory based on the back gate structure of an FDSOI device. Background technique [0002] Static random access memory (SRAM) is widely used in microprocessors and SoC chips due to its advantages of saving information without refreshing, stable data storage, fast read and write speed, and low power consumption. In order to obtain better performance, in microprocessors and SoC systems, the area occupied by memory continues to increase. According to the International Technology Roadmap For Semiconductors (ITRS), it is predicted that more than 90% of the entire SoC chip will be in the future. area is occupied by memory. Therefore, as the SRAM storage unit occupying the largest area in the SoC chip, its power consumption, stability and area size affect various performance indicators of the entire chip, and thus gra...

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Problems solved by technology

[0003] After the process is scaled down to the deep nano-node, the impact of process fluctuations, mainly including random doping fluctuations, oxide layer thickness fluctuations, and edge roughness fluctuations on the scribe line, on the stability of data in SRAM cannot be ignored, which greatly reduces the Yield of SRAM

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