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Method and system for determining overlay deviation

A technology of overlay deviation and determination method, which is applied in the field of overlay deviation determination method and system, can solve problems such as uneven stress distribution, reduced wafer yield, and no solution is proposed, so as to save process cost and product technology. Stable and accurate, the effect of improving product yield

Active Publication Date: 2022-06-21
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the number and thickness of the device continue to increase, the stress distribution between the center and edge of the wafer, each exposure area (Shot) and each die (Die) will become uneven
At this time, there will be a significant difference between the conditions in the scribe line and the grain, and the overlay mark on the scribe line alone cannot accurately reflect the actual situation of the overlay deviation in the die. If the overlay mark on the scribe line is still used for measurement and Compensation, there will be a great risk of compensating the alignment accuracy of the overlay in the die to be worse, which will have a great impact on the stability of the lithography process and product process, which will lead to a serious decrease in the yield of the wafer
[0004] For the above-mentioned problems existing in related technologies, no effective solution has been proposed yet

Method used

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  • Method and system for determining overlay deviation
  • Method and system for determining overlay deviation
  • Method and system for determining overlay deviation

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Embodiment Construction

[0024] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be further elaborated below in conjunction with the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations of the present application. All other embodiments obtained without creative work fall within the scope of protection of the present application.

[0025] In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same or a different subset of all possible embodiments, and Can be combined with each other without conflict.

[0026] If there is a similar description of "first / second" in the application documents, the following description will be added. In the following description, the term "first\second\third" involved is only to distinguish simil...

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Abstract

The embodiment of the present application discloses a method and system for determining an overlay deviation, wherein the method includes: during the process of performing a photolithography process on each layer of wafer, within each crystal grain on the mask pattern , setting an overlay mark along the middle of the sideline of the cell array area; during an overlay alignment operation, the overlay mark of the current layer and the overlay mark of the previous layer of the current layer are measured by a measuring device , to determine the overlay deviation between the current layer and the previous layer.

Description

technical field [0001] The present application relates to, but is not limited to, the field of semiconductor manufacturing, and in particular, relates to a method and system for determining overlay deviation. Background technique [0002] Three-dimensional NAND (3D NAND) memory is a popular device in the field of semiconductor memory at present. It adopts a device structure of vertically stacked multi-layer memory cells, which reduces the unit cost of memory cells while achieving extremely high data storage density. Due to the multi-layer stacking involved in the device structure, photolithography and alignment of the multi-layers are required in the process of the 3D NAND memory. [0003] In the related art, in order to monitor the alignment accuracy of the overlay (OVL) of each layer process, the monitoring of the product process is realized by placing the overlay mark on the cutting road for measurement, and the alignment of the overlay according to the measured overlay d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/20
CPCG03F7/70633H01L23/544H01L22/12H01L22/20H01L2223/54426Y02P70/50
Inventor 郭芳芳陆聪李伟卢绍祥轩攀登
Owner YANGTZE MEMORY TECH CO LTD