Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a substrate, forming a gate structure on the substrate, forming a source-drain doped layer in the substrate at two sides of the gate structure, forming a dielectric layer on the substrate exposed by the gate structure, and enabling the dielectric layer to cover the top of the gate structure; forming first contact holes exposing the top of the source-drain doped layer in the dielectric layer on two sides of the gate structure; forming a first conductive layer electrically connected with the source-drain doped layer in the first contact holes, wherein the top of the first conductive layer is lower than the top of the gate structure; forming a side wall layer onthe side wall of each first contact hole exposed out of the first conductive layer after the first conductive layer is formed; and forming a second conductive layer in each first contact hole after the side wall layer is formed, wherein the second conductive layer and the first conductive layer are used for forming a first contact hole plug. According to the embodiment of the invention, the contact resistance between the first contact hole plug and the source-drain doped layer is facilitated to be reduced, the breakdown voltage between the first contact hole plug and the gate structure is improved, and the electrical performance of the semiconductor structure is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for the integration and performance of integrated circuits are becoming higher and higher. In order to improve the integration level and reduce the cost, the critical dimensions of the components are becoming smaller, and the circuit density inside the integrated circuit is increasing. This development makes the wafer surface unable to provide enough area to make the required interconnection lines. [0003] In order to meet the requirements of interconnect lines after the critical dimension has been shrunk, the current conduction between different metal layers or the metal layers and the substrate is achieved through an interconnect structure. The interconnect struct...

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Problems solved by technology

[0005] Due to the continuous reduction of the critical dimensions of the device, the distance between the source-drain doped layer and the gate structure is continuously reduced, and the distance between the contact hole plug electrically connected to the source-drain doped layer and the gate structure is also continuously reduced. Therefore, It is easy to reduce the breakdown voltage between the contact hole plug and the gate structure, thereby adversely affecting the electrical performance of the semiconductor structure

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