Test planning system and method based on hypercube topological structure in network-on-chip

Abstract

The invention discloses a test planning system and method based on a hypercube topological structure in a network-on-chip. The system comprises an IP core extraction module, an IP core coding module,an input port distribution module, a path algorithm module, an output port distribution module and a data analysis module. The IP core extraction module is used for extracting a test IP core in the circuit to be tested and parameters required by the test; an IP core is coded and mapped by a hypercube structure through an IP core coding module; a test vector is distributed to a specified port by the input port distribution module, then the path algorithm module plans a path by using an E-cube algorithm with partial adaptive capacity and tests an IP core, and a test result is planned by the E-cube algorithm with partial adaptive capacity and sent to the output port distribution module. By reducing the number of routers passed in the test process, the distance between IP cores and the diversity of routing node selection in the data transmission process, the test time of the IP cores is reduced, and the test efficiency is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit testing, in particular to a test planning system and method based on a hypercube topology in an on-chip network. Background technique [0002] The specific test process of the on-chip network is as follows: first, the test vector enters the topology structure from the input port, is transmitted to the IP core to be tested by a certain routing strategy and waits for the test to be completed, and then the test response of the IP core passes through the topology structure again with a certain routing algorithm Transfer to output port for analysis. [0003] The topology reflects the connection and layout of communication nodes, which will affect the communication delay and network throughput of the network on chip; the routing algorithm determines the transmission path of the message in the network, and a good routing algorithm can improve the performance of the interconnection network. At present, ...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a test planning system and method based on a hypercube topology in an on-chip network, aiming to solve the problem of low test efficiency caused by the long time spent in the process of testing the on-chip network using traditional structural algorithms

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