Field effect transistor source-drain resistance extraction method

Abstract

The invention discloses a field effect transistor source-drain resistance extraction method comprising the steps: 1, testing to obtain a first electrical characteristic curve formed by absolute valuesof drain current and gate voltage of a linear region of a field effect transistor, and extracting threshold voltage of the linear region; 2, selecting a plurality of sampling points in a high gate voltage region, and calculating reciprocals of absolute values of difference values between gate voltages corresponding to the sampling points and threshold voltages of the linear region to serve as first parameters; 3, calculating the ratio of the drain voltage to the drain current of each sampling point and taking the ratio as the total resistance; 4, forming a second relation curve according to the first parameter of each sampling point and the total resistance; and 5, extending the second relation curve and intersecting the second relation curve with the longitudinal axis, and taking the intercept as the source-drain resistance. Source and drain resistors can be extracted for a single transistor, the method is suitable for field effect transistors with uniformly or non-uniformly doped channels, the test area is saved, the test speed is improved, and the resistance extraction precision is improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for extracting the source-drain resistance of a field effect transistor. Background technique [0002] Such as figure 1 Shown is a schematic diagram of the composition of the total resistance of a field effect transistor; the field effect transistor includes a source region 102 , a drain region 103 , a channel region and a gate structure 104 . figure 1 In , the source region 102 is also represented by Source, the drain region 103 is also represented by Drain, and the gate structure 104 is also represented by Gate. [0003] The source region 102 and the drain region 103 are formed in the semiconductor substrate 101 on both sides of the gate structure 104, and the channel region is located between the source region 102 and the drain region 103 and is The area covered by the gate structure 104 . [0004] The source region 102 is connected t...

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Problems solved by technology

However, the premise of using this existing extraction method is to assume that the transistor channel is uniformly doped

However, in short-channel devices, the halo effect in shallow doping technology, that is, the formation of the halo implantation region will cause uneven channel doping of the transistor, and the method of using the gate length array to extract the source-drain resistance will bring big error

Secondly, this method needs to design and layout several transistors with different channel lengths, which not only occupies the chip area, but also makes the test time doubled according to the transistor data, which is a waste of space and time

Finally, for a particular transistor, this method cannot extract the source-drain resistance of a single transistor

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