Method of fabricating magnetic random access memory cell array
A random access memory and cell array technology, applied in the manufacture/processing of electrical components, electromagnetic devices, semiconductor/solid-state device manufacturing, etc., can solve problems such as shortening, damage to MRAM performance, write voltage or current fluctuations, etc.
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Embodiment 1
[0053] A method for making a magnetic random access memory cell array of the present invention provides a method for making an ultra-small size magnetic memory cell array, through a bottom electrode through hole (BEV) and a metal connection Mx (x ≥ 1) Or make a layer of non-Cu bottom electrode via contact (Bottom Electrode VIA Contact, BEVC) between the metal vias Vx (x≥1) to solve the problem of bottom electrode vias and metal wiring Mx (x ≥1) or a series of problems arising from the continuous deterioration of the contact resistance of the metal via Vx (x≥1).
[0054] More specifically, since the bottom electrode via contact (BEVC) is made of non-Cu metal, there is enough over-etch space when making the bottom electrode via (BEV), and there will be no gap between the BEVC and the BEV. Residues with poor conductivity are left; at the same time, since the bottom electrode through-hole contact (BEVC) does not become significantly smaller as the critical dimension of the MTJ bec...
Embodiment 2
[0098] The main difference between the second embodiment and the first embodiment is that another solution of the first step is provided, and the rest is the same as the first embodiment.
[0099] Step 1: Provide a surface-polished CMOS substrate 100 with a metal connection line Mx (x≥1) or a metal through hole Vx (x≥1), and make a bottom electrode via contact (BEVC, Bottom Electrode Via Contact) thereon ), its material can be TaN, Ta, Ti, TiN, Co, W, Al, WN, Ru or their combination.
[0100] Figure 3(a) is a schematic diagram of step 1.2.1 in Embodiment 2 of the present invention;
[0101] Figure 3(b) is a schematic diagram of step 1.2.2 in Embodiment 2 of the present invention;
[0102] Figure 3(c) is a schematic diagram of step 1.2.3 in Embodiment 2 of the present invention;
[0103] Fig. 3(d) is a schematic diagram of step 1.2.4 in the second embodiment of the present invention.
[0104] Its formation steps can specifically be:
[0105] 1.2.1: Deposit a layer of dielec...
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