DAC multi-chip synchronous design based on group delay filter

Abstract

The invention provides a DAC multi-chip synchronization scheme and a circuit based on a group delay filter. The synchronization scheme comprises a plurality of DAC chips integrated with group delay filters and a time-to-digital converter, a D trigger, an N1-time frequency divider, an N2-time frequency divider, a DA data processor, a group delay filter and a DA converter module are arranged in theDAC chip. A synchronous control signal SYNCOUT generated in the DAC is used for detecting the phase difference of each DAC chip, the integer of a group delay filter and the delay value of a decimal delay unit are dynamically adjusted, and the phase difference caused by asynchronous transmission delay between clock signals CLK of the DAC chips is eliminated.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to a multi-chip DAC synchronization technology. Background technique [0002] DAC is an important bridge connecting the analog world and the digital world. It is widely used in computer, communication, instrumentation, radar, electronic countermeasures and other fields. As the system requires higher and higher bandwidth and resolution, the application of DAC has been promoted to The development of the array form requires real-time synchronization and phase control for each DAC chip that makes up the array. [0003] In a high-speed phased array system, the delay error of the clock between channels and the initial phase uncertainty of the frequency division circuit are the two main factors that determine the synchronization of DAC multi-chips. The traditional DAC multi-chip synchronous calibration scheme first uses the synchronous control input signal SY...

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Problems solved by technology

[0004] There are two deficiencies in the traditional multi-chip synchronization scheme: one is that the phase detection of the DAC output signal is required. Since the signal is an analog signal, a high-precision analog-to-digital converter or an analog phase detector is required, and the phase detection circuit is relatively complicated; the other is If only the SYNCIN signal is adjusted, the phase adjustment accuracy is only an integer number of clock CLK cycles. If the CLK delay is adjusted, no matter whether the on-chip or off-chip solution is used, noise will be introduced into the clock chain, which will deteriorate the DAC output noise. floor and phase noise

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