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Zero overhead computer interrupts with task switching

A microcomputer and task technology, applied in calculation, program startup/switching, program control design, etc., can solve problems not suitable for low energy consumption and cooling expenditure single chip, overall structure processing, etc., to avoid line and capacity delay, low Processing power, easy to design effects

Inactive Publication Date: 2003-07-30
齐龙
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, they are generally not suitable for monolithic, monolithic structural processing, which offers advantages in terms of cost, low energy and cooling expenditure, and increased performance

Method used

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  • Zero overhead computer interrupts with task switching
  • Zero overhead computer interrupts with task switching
  • Zero overhead computer interrupts with task switching

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Embodiment Construction

[0052] figure 1 A bit slice for a task register of computer 1 is schematically shown. Each 32-bit register uses 32 such slices. Typically, CPUs use multiple 32-bit registers. CPU1 and Static Random Access Memory (SRAM) 2 can alternately be connected to latch 3 and latch 4 (never connected to the same latch). For the sake of discussion, let's start with latch 3, which is connected to the CPU, and latch 4, which is connected to SRAM2. In this configuration, the CPU executes the tasks stored in latch 3. While CPU1 is running a program that uses task latch 3, the hardware handles interrupts in the background.

[0053] Fig. 3 schematically shows an interrupt processing circuit. Hardware interrupt 90 contains all possible hardware interrupt sources, including external probes, internal peripherals, and exception generators. In a preferred embodiment, each major interrupt source is assigned a fixed hardware task number. Alternatively, soft mapping between hardware and sources a...

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Abstract

The invention constitutes a unique hardware zero overhead interrupt and task change system for the reduction or elimination of interrupt latency as task change processing overhead delays in computer architectures. Without loss of time, the system performs complete task state saving and restoration between one cycle and the next without software intervention. For each Central Processing Unit (1) the invention uses one or more auxiliary latches (3, 4) wherein one latch (4) is used as the 'running' latch and one of the auxiliary latches is attached to task storage memory. The invention swaps connections between alternate 'running' registers and auxiliary registers while transferring other tasks to and from task storage memory (2). The invention provides a task linking system to allow the linking of tasks for mandatory sequential execution of the linked tasks. Further, the invention includes a priority 'impatience' counter system to increase the relative priorities of various tasks as they approach their task deadlines.

Description

[0001] Technical solutions [0002] The invention relates to an interrupt processing and task switching circuit and method in a data processing system. Background technique [0003] Modern computers use special hardware to automate interrupt handling and task switching. Interrupts include events such as I / O transfers, clocks, hardware faults, software interrupts, and software faults such as division by zero. In order for the interrupt program not to change the running program, the state of all interrupted tasks must be saved. Then, all new interrupt task states must be retrieved from memory and continue to be processed. Once the interrupt task is completed, the interrupt return instruction is usually executed, and the state saving process is executed to restore itself and resume the previous task. [0004] Most modern computers implement the task transition process using a hardware interrupt mechanism that first disables further interrupts and saves only a minimal number of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/46G06F9/48
CPCG06F9/462G06F9/06G06F9/30G06F9/48
Inventor 布赖恩·多诺万
Owner 齐龙
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