esd protection circuit and electronic device

An ESD protection and circuit technology, applied in the direction of emergency protection circuit devices, electric solid state devices, circuits, etc., can solve problems such as difficult performance improvement, and achieve the effect of avoiding quality and preventing leakage current

Active Publication Date: 2021-11-12
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, there are limitations in the circuit structure of existing ESD protection circuits, making it difficult to improve the performance

Method used

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  • esd protection circuit and electronic device
  • esd protection circuit and electronic device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0031] In the prior art, when a clamp transistor is used to form an ESD protection circuit, the active circuit of the N-type clamp transistor is often driven by the gate, and the clamp transistor is coupled between the power supply terminal and the ground terminal. Core devices are protected.

[0032] refer to figure 1 , figure 1 It is a schematic circuit structure diagram of an ESD protection circuit in the prior art. The ESD protection circuit can be used to protect the circuit 17 to be protected, and can also include:

[0033] power terminal;

[0034] ground terminal;

[0035] The discharge path includes a clamping transistor 15, the clamping transistor 15 is an N-type transistor, and the source of the clamping transistor 15 is connected to the power supply terminal, and the drain of the clamping transistor 15 is connected to the The ground terminal, and the substrate terminal of the clamp transistor 15 is connected to the source;

[0036] a first resistor 11, the fir...

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PUM

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Abstract

An ESD protection circuit and an electronic device, the ESD protection circuit includes: a power supply terminal; a ground terminal; and different types: the source and drain of the clamping transistor are electrically connected to the substrate terminal, and are connected to the power supply terminal; the gate of the MOS transistor is electrically connected to the substrate terminal; the The first pole of the MOS transistor is electrically connected to the gate of the clamping transistor, and the second pole of the MOS transistor is connected to the ground terminal; wherein, when ESD occurs, the MOS transistor is turned on, forming the A parasitic current between the substrate terminal of the transistor and the second pole is clamped. The solution of the present invention can better prevent the leakage path from generating leakage current and avoid affecting the quality of the core device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an ESD protection circuit and an electronic device. Background technique [0002] With the rapid development of the semiconductor manufacturing process, devices with ultra-thin gate oxide layers and thin dielectrics are increasing, and the electrostatic discharge (Electro-Static Discharge, ESD) problem has gradually become one of the main factors of chip failure. Taking Fin Field Effect Transistor (FinFET) as an example, in the face of the high leakage problem of multiple Fin structures, the ESD protection circuit inside the chip is indispensable. [0003] In the prior art, there already exists a protection scheme that adopts a clamp circuit (Clamp Circuit) including a clamp transistor (Clamp Transistor) as an ESD protection circuit. Specifically, the ESD protection circuit drives an N-type An active circuit of a clamping transistor, and the clamping transistor is coupled...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02H9/04
CPCH02H9/046H01L27/0262H01L27/0285H01L27/092H01L27/0277H01L27/0288H03K17/08104
Inventor 陈光陈捷
Owner SEMICON MFG INT (SHANGHAI) CORP
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