Silicon connection layer test circuit for testing by using test bare chip

Abstract

The invention provides a silicon connection layer test circuit for testing by using a test bare chip and belongs to the technical field of semiconductors. JTAG control logic and a boundary scanning test chain are arranged in the test bare chip to form a test circuit; connecting points with the same arrangement mode are arranged on the surfaces of the test bare chip and a silicon connecting layer,so that when the test bare chip is arranged on a carrier and is attached to the surface of the silicon connecting layer, butt joint between the connection points can be realized, therefore, test excitation transmission and test result capture of a signal path structure in the silicon connecting layer can be completed by using the test circuit in the test bare chip; the silicon connecting layer canbe easily tested so as to be rapidly screened before assembly, it is guaranteed that the silicon connecting layer with normal functions and bare chips can be assembled to form a normal multi-bare-chip silicon stacking interconnection structure in a later period, and therefore the production yield is guaranteed.

Description

Technical field [0001] The invention relates to the field of semiconductor technology, in particular to a silicon connection layer test circuit that utilizes test bare chips for testing. Background technique [0002] FPGA (Field Programmable Gate Array, Field Programmable Gate Array) is a hardware programmable logic device. In addition to being used in mobile communications, data centers and other fields, it is also widely used in prototype verification in integrated circuit design and can be effectively verified. The correctness of the circuit function, while speeding up the circuit design speed. Prototype verification needs to use the programmable logic resources inside the FPGA to realize circuit design. With the continuous increase of the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources of the FPGA continues to increase, and subsequent technological development and demand With the continuous incr...

AI Technical Summary

Problems solved by technology

Prototype verification requires the use of programmable logic resources inside the FPGA to implement circuit design. With the continuous increase in the scale of integrated circuits and the realization of complex functions, the demand for the number of programmable logic resources in FPGAs continues to increase. Subsequent technology development and demand As the number of FPGA programmable resources continues to increase, it will become a greater bottleneck, posing greater challenges to the development of the industry

The increase in FPGA scale means that the chip area continues to increase, which will lead to an increase in the difficulty of chip processing and a decrease in chip production yield.

[0003] At present, some patents have proposed a method of chip interconnection design through silicon stacked interconnection technology (SSI). Later, it was discovered that the function of the silicon connection layer was abnormal and the entire FPGA was affected, and the production yield was difficult to guarantee.

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