Manufacturing method of three-dimensional memory
A manufacturing method and memory technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve the problem of damage to the functional layer, failure of the storage function of the three-dimensional memory, easy misalignment between the second channel hole and the first channel hole, etc. problem, to achieve the effect of improving yield and reliability
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Embodiment 1
[0094] figure 1 It is a schematic structural diagram of a three-dimensional memory in an embodiment of the present invention; as figure 1 As shown, the three-dimensional memory provided by the embodiment of the present invention includes a substrate 10, and the substrate 10 can be made of a semiconductor material, and the manufacturing material of the substrate 10 includes but not limited to silicon, germanium, silicon germanium, etc. Made of single crystal silicon.
[0095] A stack structure 40a is disposed on the substrate 10; for example, a first stack structure 41a and a second stack structure 42a are sequentially disposed on the substrate 10, that is, the second stack structure 42a is located above the first stack structure 41a. Both the first stack structure 41a and the second stack structure 42a include a plurality of insulating layers and a plurality of gate layers alternately arranged; wherein, the thickness of the gate layer and the thickness of the insulating layer...
Embodiment 2
[0161] Figure 23 It is a schematic structural diagram of the three-dimensional memory in the second embodiment of the present invention; it should be noted that the structure of the three-dimensional memory provided in the second embodiment is the same as the structure of the three-dimensional memory provided in the first embodiment, and will not be repeated here. The difference between the structure of the three-dimensional memory provided in the second embodiment and the three-dimensional memory provided in the first embodiment is that, in the second embodiment, the etching barrier layer 30 and the substrate 10 are provided with the closest substrate The gate layer of the bottom 10 (that is, the first gate layer 25 located between the substrate 10 and the etch stop layer 30 in Embodiment 1), and the first channel structure 61 passes through the gate closest to the substrate 10 The gate layer extends into the substrate 10 , and a semiconductor layer 26 is provided on both si...
Embodiment 3
[0200] Figure 38 A schematic structural diagram of a three-dimensional memory provided in Embodiment 3 of the present invention; as Figure 38 As shown, the three-dimensional memory provided by this embodiment includes a substrate 10 and a first stack structure 41a and a second stack structure 42a disposed on the substrate 10 in sequence, wherein the first stack structure 41a is located on the substrate 10, and the second stack structure 42a is disposed on the substrate 10. The stack structure 42a is located on the first stack structure 41a, and the first stack structure 41a is provided with a first channel structure 61 perpendicular thereto, and one end of the first channel structure 61 close to the substrate 10 can extend to the end of the substrate 10 On the surface, the end of the first channel structure 61 away from the substrate 10 is electrically connected to the second channel structure 62 .
[0201] The structure of the first channel structure 61 and the second chan...
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Abstract
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