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Preparation method of semiconductor structure

A technology of semiconductor and plasma gas, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as difficult to remove, affect device performance, test failure, etc.

Active Publication Date: 2020-10-20
南京晶驱集成电路有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] At present, in the process of manufacturing some flash memories, for example, when making gate structures, a dielectric layer is usually grown on the surface and sidewalls of polysilicon. In the process of etching polysilicon, since the dielectric layer is grown on polysilicon Around the layer, the dielectric layer on the sidewall of the polysilicon layer is relatively high, which is equivalent to a fence. When etching polysilicon, it is difficult to remove the polysilicon at the corner of the dielectric layer on the sidewall of the polysilicon layer. If it is completely removed, there will be polysilicon residues, which will cause short circuits in the subsequent semiconductor structures, resulting in test failures and affecting device performance.

Method used

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Embodiment Construction

[0048] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual impleme...

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Abstract

The invention discloses a preparation method of a semiconductor structure. The preparation method at least comprises the following steps of providing a substrate, forming a gate oxide layer on the substrate, forming a first polycrystalline silicon layer on the gate oxide layer, forming a dielectric layer on the surface of the first polycrystalline silicon layer and the gate oxide layer, wherein the dielectric layer forms a fence structure on the side wall of the first polycrystalline silicon layer, forming a second polycrystalline silicon layer on the dielectric layer, etching for the first time, removing part of the second polycrystalline silicon layer by etching for the first time, and taking the dielectric layer as a stop layer, and etching for the second time, wherein the dielectric layer on the first surface of the first polycrystalline silicon layer is removed by etching for the second time. The performance stability of the semiconductor device can be improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preparing a semiconductor structure. Background technique [0002] At present, in the process of manufacturing some flash memories, for example, when making gate structures, a dielectric layer is usually grown on the surface and sidewalls of polysilicon. In the process of etching polysilicon, since the dielectric layer is grown on polysilicon Around the layer, the dielectric layer on the sidewall of the polysilicon layer is relatively high, which is equivalent to a fence. When etching polysilicon, it is difficult to remove the polysilicon at the corner of the dielectric layer on the sidewall of the polysilicon layer. If it is completely removed, there will be polysilicon residues, which will cause a short circuit in the subsequent semiconductor structure, resulting in test failure and affecting device performance. Contents of the invention [0003] In view ...

Claims

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Application Information

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IPC IPC(8): H01L21/28H01L27/11521H01L27/11568
CPCH01L21/28008H10B41/30H10B43/30
Inventor 林祐丞杨智强林子荏林政纬
Owner 南京晶驱集成电路有限公司
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