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Method for testing signal transmission delay in FPGA chip

A signal transmission and chip technology, which is applied in the field of signal transmission delay testing in FPGA chips, can solve the problems of area consumption and cost increase

Active Publication Date: 2020-10-23
SHANGHAI FUDAN MICROELECTRONICS GROUP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, in order to fully simulate the delay in the circuit, it is necessary to design multiple test circuits at the same location, which will also consume area and increase cost

Method used

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  • Method for testing signal transmission delay in FPGA chip
  • Method for testing signal transmission delay in FPGA chip
  • Method for testing signal transmission delay in FPGA chip

Examples

Experimental program
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Embodiment Construction

[0022] based on the following Figure 4 ~ Figure 9 , specifically explain the preferred embodiment of the present invention.

[0023] The FPGA chip includes a configurable logic module CLB (Configurable Logic Block), an input / output module (I / O module) and a programmable interconnection line. The programmable interconnection line realizes between CLB modules, between I / O modules, and CLB modules and the connection between the I / O module. CLB modules, I / O modules and programmable interconnection lines all contain SRAM (Static Random Access Memory, static random access memory). Before using the FPGA chip, you need to download the bit stream file. The bit stream file describes the SRAM in the FPGA chip. The value can be changed flexibly. By changing the value in the SRAM in the CLB module, different logic functions can be realized, such as various combinational logic functions such as AND gate, OR gate, and NOT gate. By changing the value in the SRAM in the programmable interc...

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Abstract

The invention provides a method for testing signal transmission delay in an FPGA chip. According to the method, at least one CLB module and at least one I / O module are connected into a ring oscillatorthrough a programmable interconnection line, the number of the CLB modules in the ring oscillator is an odd number, and LUT modules in the CLB modules are configured to be NOT gate circuits. According to the invention, logic resources and interconnection resources of the FPGA chip are directly utilized for a signal transmission delay test, so extra expenditure for circuits is avoided, and a circuit area is saved; and the test method is very flexible and accurate, and can support tests at various positions and tests of various transistor types.

Description

technical field [0001] The invention relates to a method for testing signal transmission delay in an FPGA chip. Background technique [0002] FPGA (Field Programmable Logic Array) is an integrated circuit chip that includes a configurable logic module CLB (Configurable Logic Block), an input / output module (I / O module) and a programmable interconnect PI (Programmable Interconnect). For FPGA chips of different specifications, they can contain 8×8, 20×20, 44×44 or even 92×92 CLB arrays, and are equipped with 64, 160, 352, or even 448 I / O modules and programmable Other components necessary for wiring. [0003] The performance of an integrated circuit is mainly judged by the transmission delay of the signal. Such as figure 1 As shown, the first way to test the transmission delay is to analyze the transmission delay of the signal through an independent test system. Due to the large number of chips being fabricated simultaneously on a single wafer, there are scribe lines betwee...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/317G01R31/3185G01R31/3187
CPCG01R31/31725G01R31/318519G01R31/3187Y02D10/00
Inventor 谈佳瑛俞剑陈宁徐烈伟沈鸣杰
Owner SHANGHAI FUDAN MICROELECTRONICS GROUP