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Controllable multi-beam forming method based on FPGA

A multi-beam and beam technology is applied in the field of FPGA-based controllable multi-beam forming, which can solve the problem of insufficient real-time flexibility of beam control, and achieve the effects of improving resource utilization, expanding application scope and reducing resource consumption.

Active Publication Date: 2020-10-23
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method relies on receiving external weight input for weighting calculations, and does not involve the real-time calculation function of multi-beam weights. The real-time flexibility of beam control is not high enough, and it does not involve anti-interference measures.

Method used

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  • Controllable multi-beam forming method based on FPGA
  • Controllable multi-beam forming method based on FPGA
  • Controllable multi-beam forming method based on FPGA

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Experimental program
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Embodiment

[0190] In this example, there are 4×4=16 array elements, and the maximum number of beams that can be formed within the FPGA resource constraints is N max to 16. At a certain moment, the radar needs to form 4 beams in the same time and work in the anti-jamming mode S2.

[0191] Step 1: Schedule frame protocol information input and frame analysis

[0192] When the FPGA is powered on, all registers are set to 0 by default, and the FIFO and RAM are empty, which is consistent with the state after reset.

[0193] Enter a frame of beam followed by a new command. The frame structure is defined as 20 bytes, the first to second bytes are the frame header length=0x14, the third byte is the function code Fcode=0x10, the fourth byte is the number of beams K=0x04, the fifth to The 6 bytes are the first beam azimuth and elevation respectively. Bytes 7 to 8, 9 to 10, and 11 to 12 are the azimuth and elevation angles corresponding to the second, third, and fourth beams, respectively. The ...

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Abstract

The invention belongs to the technical field of array signal processing, and particularly relates to a controllable multi-beam forming method based on an FPGA. According to the controllable multi-beamforming method based on the FPGA, corresponding beam data can be controlled to be generated according to a scheduling frame protocol input angle, a conventional beam forming function and an adaptivebeam forming function are integrated, the adaptive beam forming solves a beam weight in an iterative manner, covariance matrix inversion operation is avoided, the real-time performance of weight calculation is improved, an iterative module has universality, and multi-beam weight calculation can be completed through parallel multiplexing. The weighting output end performs multi-beam weighting in aparallel pipeline mode to generate beam pointing at an expected angle.

Description

technical field [0001] The invention belongs to the technical field of array signal processing, and in particular relates to a controllable multi-beam forming method based on FPGA. Background technique [0002] In order to expand the scanning range of the airspace and improve the detection efficiency of the phased-array radar, the phased array radar can adopt the simultaneous multi-beam forming technology. The FPGA-based DBF design has the advantages of high data processing parallelism, fast operation speed, and small hardware size, and is suitable for multi-beamforming processing of large-scale arrays. [0003] Liu Ying, Wei Wei and others designed a general DBF module for 2D beamforming in "FPGA-based Large Scale Two-Dimensional Area Array Digital Beamforming". Save multiplier resources and improve module reuse. However, this method needs to calculate the module multiplexing amount and beam coverage in advance according to the radar data rate. When the weight coefficient...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01S13/02G01S7/02G01S7/285G01S7/35H04B7/0426
CPCG01S13/02G01S7/02G01S7/352G01S7/285H04B7/043G01S2013/0245Y02D30/70
Inventor 宗竹林罗杰
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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