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National cryptographic algorithm SM4 acceleration processing method and system based on high-level integration

A high-level synthesis and national secret algorithm technology, applied in the embedded field of national secret algorithm, can solve problems such as slow running speed, long hardware development time, and insufficient flexibility of embedded platforms, so as to reduce time cost, reduce development time, The effect of reducing the time to achieve

Active Publication Date: 2020-11-10
SHANDONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In order to solve the problems of insufficient flexibility, slow running speed and long hardware development time of the existing SM4 algorithm embedded platform, this application provides a national secret algorithm SM4 accelerated processing method and system based on high-level synthesis;

Method used

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  • National cryptographic algorithm SM4 acceleration processing method and system based on high-level integration
  • National cryptographic algorithm SM4 acceleration processing method and system based on high-level integration
  • National cryptographic algorithm SM4 acceleration processing method and system based on high-level integration

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Experimental program
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Effect test

Embodiment 1

[0043] This embodiment provides an accelerated processing method based on high-level synthesis of the national secret algorithm SM4;

[0044] Such as figure 1 As shown, based on the high-level comprehensive national secret algorithm SM4 accelerated processing method, the data packets sent to the server to be processed by the national secret algorithm are processed, including:

[0045] S101: Using the high-level integrated HLS to realize the national secret algorithm SM4 through the high-level programming language; perform simulation processing on the high-level programming language;

[0046] S102: After the simulation process passes normally, perform synthesis to obtain a comprehensive report, and observe the performance of the national secret algorithm through the comprehensive report; use high-level comprehensive HLS to optimize the national secret algorithm SM4, and finally export the IP core through joint simulation, so that High-level comprehensive HLS automatically real...

example 1

[0084] Example 1-realization based on the disclosed SM4 algorithm:

[0085] The implementation of the present disclosure will be described below in conjunction with the accompanying drawings. The design, implementation and acceleration method of the SM4 algorithm based on high-level synthesis described in this implementation, the specific process is as follows:

[0086] First of all, E1 implements the SM4 algorithm through C language. This algorithm has multiple functions to implement, but in this example, in order to describe the problem simply, the algorithm is used as a function, and the input is all fixed length, such as unsigned long*sk, unsigned char*input, unsigned char*output, although the parameters of the function are in the form of pointers, in fact, unsigned long*sk is a 1024bit extended key in the form of unsigned long sk[32] in an encryption process, the same unsigned char *input, unsigned char*output is 128bit input and output information in the form of unsigned...

Embodiment 2

[0111] Such as Figure 6 , the present embodiment provides an accelerated processing system based on the high-level comprehensive national secret algorithm SM4;

[0112] Based on the high-level comprehensive national secret algorithm SM4 accelerated processing system, FPGA processes the data packets sent to the server to be processed by the national secret algorithm, including the server and FPGA;

[0113] Arrange the SM4 encrypted IP core generated by HLS on the FPGA, use python to call the IP core, and encapsulate it into an SM4 encrypted function;

[0114] FPGA reads the data packets to be processed by the national secret algorithm from the server memory;

[0115] Call the SM4 encryption function through python to realize the processing of the data packets to be processed by the national secret algorithm, and form the data packets processed by the national secret algorithm;

[0116] The FPGA transmits the data packets processed by the national secret algorithm to the memo...

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Abstract

The invention discloses a national cryptographic algorithm SM4 acceleration processing method and system based on high-level integration. FPGA processes a to-be-processed data packet transmitted to aserver through a national cryptographic algorithm. An SM4 encrypted IP core generated by an HLS is arranged on the FPGA. The IP core is called through python, and the IP core is packaged into an SM4 encryption function; the FPGA reads the to-be-processed data packet by the national cryptographic algorithm from a server memory; the SM4 encryption function is called through python to process the to-be-processed data packet by the national cryptographic algorithm, and the data packet processed by the national cryptographic algorithm is formed; and the FPGA transmits the data packet processed by the national cryptographic algorithm to the memory of the server.

Description

technical field [0001] This application relates to the field of national secret algorithm embedded technology, in particular to a method and system for accelerated processing of national secret algorithm SM4 based on high-level synthesis. Background technique [0002] The statements in this section merely mention the background art related to this application, and do not necessarily constitute the prior art. [0003] The National Secret Algorithm is a series of algorithms formulated by the State Cryptography Administration. These include symmetric encryption algorithms, elliptic curve asymmetric encryption algorithms, and hash algorithms. Specifically include SM3, SM4 and so on. National secret algorithms are widely used in data encryption, digital signature and other scenarios. Due to the country's emphasis on information security, national secret algorithms are now widely used. How to run the national secret algorithm quickly, with high performance and low power consum...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/76G06F30/20G06F115/08
CPCG06F21/76G06F30/20G06F2115/08
Inventor 刘国霄鞠雷王悦魏普文申兆岩
Owner SHANDONG UNIV