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Complementary memory cell, preparation method thereof and complementary memory

A storage unit, complementary technology, applied in the field of microelectronics, can solve the problem of storage density reduction

Active Publication Date: 2020-11-27
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] In order to solve the technical problem that in the new memory device in the prior art, CSA needs to be used for reading operation, thereby occupying the chip area and resulting in a reduction in storage density, the present invention provides a complementary memory unit, a preparation method thereof, and a complementary memory unit

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  • Complementary memory cell, preparation method thereof and complementary memory
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  • Complementary memory cell, preparation method thereof and complementary memory

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Embodiment Construction

[0029] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0030] It should be noted that, in the accompanying drawings or in the text of the specification, implementations that are not shown or described are forms known to those of ordinary skill in the art, and are not described in detail. In addition, the above definitions of each element and method are not limited to the various specific structures, shapes or methods mentioned in the embodiments, and those skilled in the art can easily modify or replace them.

[0031] It should also be noted that the directional terms mentioned in the embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only referring to the directions of the drawings, not Used to limit the protection scope of the present invention. ...

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Abstract

The invention discloses a complementary memory cell, a preparation method thereof and a complementary memory. The complementary storage unit comprises a control transistor, a pull-up diode and a pull-down diode, wherein the control transistor is used for controlling reading and writing of the storage unit; one end of the pull-up diode is connected to a positive selection line, and the other end isconnected to the source end of the control transistor for controlling high-level input; one end of the pull-down diode is connected to the negative selection line, and the other end is connected to the source end of the control transistor for controlling low-level input; wherein the pull-up diode and the pull-down diode are symmetrically arranged in the first direction. Based on the design of thecomplementary storage unit, the circuit complexity of the memory is greatly reduced, the area size of the memory is reduced, the storage density of the memory is improved, and the power consumption of the memory is also reduced under the condition that the complementary memory can realize the original functional characteristics.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a complementary memory unit, a preparation method thereof, and a complementary memory. Background technique [0002] In the current mainstream computer architecture, limited by the characteristics of storage media and technological development, multi-level storage architectures are widely used. The on-chip cache and DRAM memory read and write fast, but the storage capacity is small, and the data cannot be retained after power failure. The external memory based on the hard disk / solid state disk has a slow read and write speed, but has a large storage capacity and can retain data after power failure. The above-mentioned multi-level storage architecture causes the current computer system to frequently transfer data between different storage levels, which reduces computing efficiency. The development of high-speed, high-density non-volatile memory can effectively solve the...

Claims

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Application Information

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IPC IPC(8): G11C11/409G11C11/36G11C7/22G11C5/12
CPCG11C11/409G11C11/36G11C7/22G11C5/12Y02D10/00
Inventor 罗庆陈冰吕杭炳刘明路程
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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