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Array substrate

An array substrate and substrate technology, applied to semiconductor devices, electrical components, circuits, etc., can solve the problems of affecting the aperture ratio, increasing the leakage current, and not easily increasing the channel width/length ratio of the channel region, achieving Solve the effect of excessive leakage current and large driving current

Inactive Publication Date: 2020-12-11
TCL CHINA STAR OPTOELECTRONICS TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the increase in the width of the channel region will directly affect the aperture ratio, which is in conflict with the small TFT (thin film transistor) device with high PPI (pixel density), so the width of the channel region cannot be easily increased to increase the channel width / length ratio ; Secondly, under the condition of ensuring high driving current, manufacturers hope that the width / length ratio of the channel region will be designed in the direction of increasing, and as the length of the channel region gradually decreases, the source of TFT (thin film transistor) device and The off-state leakage current between the drains will become larger and larger (proportional to the channel width / length ratio), so there is a contradiction in the existing structure design that increases the driving current but also increases the leakage current

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Embodiment 1

[0059] see image 3 , a cross-sectional view of the array substrate provided in Embodiment 1 of the present application.

[0060] In this embodiment, the array substrate is a top-gate array substrate.

[0061] In this embodiment, the array substrate includes a substrate 10, a light-shielding layer 20 above the substrate 10, a buffer layer 30 above the light-shielding layer 20, an active layer 40 above the buffer layer 30, The gate insulating layer 50 above the active layer 40, the gate 60 above the gate insulating layer 50, the interlayer dielectric layer 70 above the gate 60, the interlayer dielectric The source 81 and the drain 82 above the electrical layer 70 , the passivation layer 90 above the source 81 and the drain 82 , and the electrode layer 100 above the passivation layer 90 .

[0062] In this embodiment, the substrate 10 is a PI substrate, mainly polyimide, and the PI material can effectively improve light transmittance.

[0063] In this embodiment, the material ...

Embodiment 2

[0106] see Figure 8 , a cross-sectional view of the array substrate provided in Embodiment 2 of the present application.

[0107] In this embodiment, the structure of the array substrate is similar / identical to the structure of the array substrate provided in the above embodiment. For details, please refer to the description of the array substrate in the above embodiment 1, which will not be repeated here. The only difference is:

[0108] In this embodiment, the array substrate is a bottom gate array substrate.

[0109] In this embodiment, the array substrate includes a substrate 10, a light-shielding layer 20 above the substrate 10, a buffer layer 30 above the light-shielding layer 20, a gate 60 above the buffer layer 30, a The gate insulating layer 50 above the gate 60, the active layer 40 above the gate insulating layer 50, the interlayer dielectric layer 70 above the active layer 40, the interlayer dielectric The source 81 and the drain 82 above the electrical layer 70...

Embodiment 3

[0120] see Figure 11 and Figure 12 , in this embodiment, the array substrate includes a substrate 10, a buffer layer 30 located above the substrate 10, a first gate 61 located above the buffer layer 30, and a gate 61 located above the first gate 61. The first gate insulating layer 51, the active layer 40 above the first gate insulating layer 51, the second gate insulating layer 52 above the active layer 40, and the second gate insulating layer A second gate 62 above layer 52 .

[0121] The array substrate further includes a source 81 and a drain 82 located above the active layer 40 and covering two opposite edge regions of the active layer 40 , located on the source 81 and the drain 82 and The passivation layer 90 above the second gate insulating layer 62 , the planar layer 110 above the passivation layer 90 , and the electrode layer 100 above the planar layer 110 .

[0122] In this embodiment, the substrate 10 is a PI substrate, mainly polyimide, and the PI material can ...

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Abstract

The invention provides an array substrate. The array substrate comprises: a substrate body; an active layer, wherein the active layer comprises a channel region; a gate insulating layer; a gate corresponding to the active layer channel region; and a source electrode and a drain electrode, wherein the source electrode and the drain electrode are arranged at two ends of the active layer. The gate adopts a groove type structure, and the opening of the groove faces the active layer; and the active layer region corresponding to the groove is the channel region. According to the invention, the gate,the gate insulating layer and the channel region corresponding to the active layer form a three-dimensional channel structure, the width of the channel region is increased in a disguised manner, under the design of the same channel region length, it is ensured that the driving current is large enough, and the high switching current ratio and the high aperture opening ratio are realized, and the safety problem of overlarge leakage current caused by reduction of the width / length ratio of a channel region and the process problem of a small channel are solved.

Description

technical field [0001] The present application relates to the field of display technology, and in particular to an array substrate. Background technique [0002] With the development of high-PPI (pixel density) OLED products, the requirements for backplanes are gradually increasing, and maintaining the performance of small-sized semiconductor devices is currently the main goal of the industry. At present, manufacturers hope to obtain OLED products with larger saturation current and better saturation characteristics, and hope that the channel region width / length is larger, the better, which means that the smaller the length of the channel region and the larger the width, the better It is beneficial to the improvement of the performance of OLED products. [0003] However, the increase in the width of the channel region will directly affect the aperture ratio, which is in conflict with the small TFT (thin film transistor) device with high PPI (pixel density), so the width of t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/12H01L27/32
CPCH01L27/1214H01L27/1222H01L27/1237H01L29/785H01L29/7853H01L29/78696H01L29/42384H01L29/7869H01L27/127H10K59/12
Inventor 黄旭
Owner TCL CHINA STAR OPTOELECTRONICS TECH CO LTD