Array substrate
An array substrate and substrate technology, applied to semiconductor devices, electrical components, circuits, etc., can solve the problems of affecting the aperture ratio, increasing the leakage current, and not easily increasing the channel width/length ratio of the channel region, achieving Solve the effect of excessive leakage current and large driving current
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Embodiment 1
[0059] see image 3 , a cross-sectional view of the array substrate provided in Embodiment 1 of the present application.
[0060] In this embodiment, the array substrate is a top-gate array substrate.
[0061] In this embodiment, the array substrate includes a substrate 10, a light-shielding layer 20 above the substrate 10, a buffer layer 30 above the light-shielding layer 20, an active layer 40 above the buffer layer 30, The gate insulating layer 50 above the active layer 40, the gate 60 above the gate insulating layer 50, the interlayer dielectric layer 70 above the gate 60, the interlayer dielectric The source 81 and the drain 82 above the electrical layer 70 , the passivation layer 90 above the source 81 and the drain 82 , and the electrode layer 100 above the passivation layer 90 .
[0062] In this embodiment, the substrate 10 is a PI substrate, mainly polyimide, and the PI material can effectively improve light transmittance.
[0063] In this embodiment, the material ...
Embodiment 2
[0106] see Figure 8 , a cross-sectional view of the array substrate provided in Embodiment 2 of the present application.
[0107] In this embodiment, the structure of the array substrate is similar / identical to the structure of the array substrate provided in the above embodiment. For details, please refer to the description of the array substrate in the above embodiment 1, which will not be repeated here. The only difference is:
[0108] In this embodiment, the array substrate is a bottom gate array substrate.
[0109] In this embodiment, the array substrate includes a substrate 10, a light-shielding layer 20 above the substrate 10, a buffer layer 30 above the light-shielding layer 20, a gate 60 above the buffer layer 30, a The gate insulating layer 50 above the gate 60, the active layer 40 above the gate insulating layer 50, the interlayer dielectric layer 70 above the active layer 40, the interlayer dielectric The source 81 and the drain 82 above the electrical layer 70...
Embodiment 3
[0120] see Figure 11 and Figure 12 , in this embodiment, the array substrate includes a substrate 10, a buffer layer 30 located above the substrate 10, a first gate 61 located above the buffer layer 30, and a gate 61 located above the first gate 61. The first gate insulating layer 51, the active layer 40 above the first gate insulating layer 51, the second gate insulating layer 52 above the active layer 40, and the second gate insulating layer A second gate 62 above layer 52 .
[0121] The array substrate further includes a source 81 and a drain 82 located above the active layer 40 and covering two opposite edge regions of the active layer 40 , located on the source 81 and the drain 82 and The passivation layer 90 above the second gate insulating layer 62 , the planar layer 110 above the passivation layer 90 , and the electrode layer 100 above the planar layer 110 .
[0122] In this embodiment, the substrate 10 is a PI substrate, mainly polyimide, and the PI material can ...
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