FPGA chip data processing method, chip, computer equipment and storage medium

A data processing and computer technology, applied in computer control, instruments, simulators, etc., can solve problems such as difficult to meet the processing requirements of high sampling rate and high bandwidth, increased PCB wiring difficulty and design cost, and difficulty in realizing IP core interconnection. , to achieve the effect of simple design, easy engineering practice, and high bandwidth processing

Inactive Publication Date: 2020-12-15
LEIHUA ELECTRONICS TECH RES INST AVIATION IND OF CHINA
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Problems solved by technology

The traditional AD front-end preprocessing has the following disadvantages: when the parallel bus is used to communicate with FPGA, there are many output pins, which leads to the difficulty of PCB layout and the increase of design cost; DDR and SDR interfaces are used in FPGA, the communication bandwidth is low, and the interface design is complicated , it is difficult to realize the interconnection between IP cores; and the serial digital down-conversion processing method is difficult to meet the processing requirements of high sampling rate and high bandwidth

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  • FPGA chip data processing method, chip, computer equipment and storage medium
  • FPGA chip data processing method, chip, computer equipment and storage medium
  • FPGA chip data processing method, chip, computer equipment and storage medium

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Embodiment Construction

[0017] Embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0018] Embodiments of the present disclosure are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Apparently, the described embodiments are only some of the embodiments of the present disclosure, not all of them. The present disclosure can also be implemented or applied through different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, a...

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Abstract

The invention provides an FPGA chip data processing method, a chip, computer equipment and a storage medium, and belongs to the field of radar AD front-end digital processing. The method particularlycomprises the following steps: receiving serial sampling data of a digital-to-analog conversion module by adopting a JESD universal interface, the sampling frequency of the serial sampling data beingnot less than 200MHz; converting the serial sampling data into multiple paths of parallel data through an IP core of the JESD universal interface; respectively carrying out frequency mixing processingon the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data; and performing filtering processing on each group of frequency mixing data to obtain low-frequency digital-analog sampling data. Through the processing scheme disclosed by the invention, the FPGA chip is simple in design, strong in processingcapacity and easy for engineering practice.

Description

technical field [0001] The invention relates to the field of radar AD front-end digital processing, in particular to an FPGA chip data processing method, chip, computer equipment and storage medium. Background technique [0002] The radar AD front-end preprocessing system is an important part of the radar system, which mainly completes the functions of intermediate frequency signal reception and baseband signal conversion. With the development of active phased array radar to large bandwidth and high integration, the system puts forward higher requirements for digital components, and light weight, small size and high bandwidth have become its important development trend. The traditional AD front-end preprocessing has the following disadvantages: when the parallel bus is used to communicate with FPGA, there are many output pins, which leads to the difficulty of PCB layout and the increase of design cost; DDR and SDR interfaces are used in FPGA, the communication bandwidth is l...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05B19/042G01S7/02
CPCG01S7/02G05B19/0423G05B2219/24215
Inventor 刘磊张强王文皞
Owner LEIHUA ELECTRONICS TECH RES INST AVIATION IND OF CHINA
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