30results about How to "Increase processing bandwidth" patented technology

Parallelization of scalar operations by vector processors using data-indexed accumulators in vector register files, related circuits, methods, and computer-readable media are disclosed. In one aspect, a vector processor comprises a vector register file providing a plurality of write ports and a plurality of vector registers each providing a plurality of accumulators. The vector processor receives an input data vector. For each of the plurality of write ports, the vector processor executes vector operation(s) for accessing an input data value of the input data vector, and determining, based on the input data value, a register index for a vector register among the plurality of vector registers, and an accumulator index for an accumulator among the plurality of accumulators of the vector register. Based on the register index, a register value is retrieved from the register index, and a scalar operation is performed based on the register value and the accumulator index.

In a method for synchronization of a mobile radio receiver to a base station, the received signal is sampled using oversampling, by which means sample values are obtained from different sampling phases. The oversampled signal is correlated with a local code, with sample values that are associated with a first sampling phase being processed with a frequency offset with respect to sample values that are associated with a second sampling phase.

The invention discloses a high performance channel simulator radio frequency transceiver applied to 5G communication. The transceiver comprises a transmission link and a receiving link, in the transmission link, an intermediate frequency signal is signally transmitted out via a first intermediate frequency, an upper mixing module, a first automatic gain amplification control module, a single-poledouble-throw switch and a radio frequency filtering module in sequence; in the receiving link, a radio frequency signal is finally received via a radio frequency filtering module, the single-pole double-throw switch, a low noise amplifier, a second automatic gain control amplification module, a lower mixing module, a second intermediate frequency filtering module and a third automatic gain amplification control module in sequence; in addition, the transceiver also comprises a local oscillator module for providing local oscillator signals to the upper mixing module and the lower mixing module.According to the transceiver provided by the invention, the complexity of the channel simulator can be effectively reduced, the requirement on power of the signal channel in 5G research is reduced, the power consumption is lowered, and meanwhile the transceiver has the characteristics of large processing bandwidth, small area and good performance.

The invention provides a data flow detection method and a data flow detection device. According to the data flow detection method and the data flow detection device, rules finally matched with a data flow are filtered, and the final remaining rules are less than the rules finally matched with the data flow, namely, the number of times of carrying out regular expression matching on the data flow finally is reduced, the performance overhead of equipment on regular expression matching is greatly decreased, and the processing bandwidth of the data flow detection equipment is broadened on the premise that hardware is unchanged.

The invention discloses an optical module and network equipment and aims to solve a problem of a relatively high processing bandwidth occupancy rate of an optical module in the prior art. The optical module is arranged at first network equipment of an access ring, the access ring comprises second network equipment and third network equipment, the second network equipment and the third network equipment are in optical connection with the first network equipment, the first network equipment is applied to an access point, the optical module comprises a first multi/demultiplexer and an optical receiver, wherein the first multi/demultiplexer is used for receiving first optical signals from the second network equipment, separating second optical signals having first wavelengths from the first optical signals and transmitting the second optical signals to the light receiver, the first multi/demultiplexer is further used for transmitting third optical signals to the third network equipment, the third optical signals are other optical signals which are separated from the first optical signals and have other wavelengths except the first wavelengths, and the light receiver is used for receiving the second optical signals.

The invention belongs to the technical field of intelligent polishing machining and manufacturing, and particularly relates to a high-order tangent contact enveloping type polishing machining controlsystem and method. The control system comprises a polishing machining parameter planning module, a workpiece pose control module, an abrasive belt compliance control module, an enveloping machining module and a polishing amount measuring module, wherein the polishing machining parameter planning module is used for identifying a convex curved surface in a workpiece curved surface, the workpiece pose control module and the abrasive belt compliance control module act cooperatively so as to adjust the pose of a workpiece and the contact force of the enveloping machining module and a sector-shapedcolumn surface in real time, and polishing machining on the workpiece is conducted under the condition; and the polishing amount measuring module is used for judging whether a polishing process is finished or not. The invention further discloses a corresponding method. According to the system, high-order cutting and enveloping on the machined workpiece are realized, meanwhile, the the workpiece pose control module and the abrasive belt compliance control module act cooperatively to achieve the synergistic effect, so that closed-loop control is realized, and the stability, rapidity and accuracyof system response are ensured.

The invention discloses an intermediate frequency signal processing unit and a digital phased array radar with the same. The intermediate frequency signal processing unit comprises a first FMC daughter board, a second FMC daughter board and a carrier board, the first FMC daughter board is provided with a first HPC connector plug, the second FMC daughter board is provided with a second HPC connector plug, and the carrier board is provided with a first HPC connector socket corresponding to the first HPC connector plug and a second HPC connector socket corresponding to the second HPC connector plug; the first FMC daughter board is provided with an ADC module, and the ADC module comprises N multi-channel ADC chips; the second FMC daughter board is provided with a DAC module, and the DAC module comprises N multi-channel DAC chips; an FPGA module and a clock module are arranged on the carrier plate, the FPGA module is electrically connected with the ADC module and the DAC module, and the clock module is electrically connected with the ADC module, the FPGA module and the DAC module. According to the intermediate frequency signal processing unit, synchronous transmission of multi-channel data can be achieved, the integration level is high, and expansion is easy.

The invention provides a graph data compression method. The method comprises the steps of obtaining original graph data and determining a node pair of each edge in the original graph data; grouping the same source nodes in the node pairs according to a preset grouping rule, wherein one source node is reserved in each group; storing the data into the corresponding FIFO according to the group type of each group; adding labels to the source node data of the source node and the destination node data of the destination node; and polling and storing the FIFO to obtain compressed graph data. According to the method, different compression ratios are adopted for the source nodes with different numbers corresponding to the destination nodes, only one source node is reserved in the same group, and repeated source nodes do not need to be stored; and large-scale parallel decompression of the graph data can be supported, and the processing bandwidth of the graph data is greatly increased. The invention further provides a data compression system of a graph calculation system, a computer readable storage medium and a data compression terminal, which have the above beneficial effects.

The invention discloses an electronic reconnaissance broadband digital receipt signal processing method based on under sampling. The method of the invention includes that: system bandwidth of a receiver is determined, and two sampling ADs are selected; according to Winograd algorithm, FFT operation is respectively carried out on the two AD acquisition signals, so as to obtain a first frequency spectrum of a first sampling AD and a second frequency spectrum of a second sampling AD; modulus of the two frequency spectrums are obtained; maximum of modulus of the two frequency spectrums and position thereof in spectral line as well as sub-maximum of modulus and position thereof in spectral line are searched, and finally frequency value of primary sinusoid component is obtained. The invention can cause the processing bandwidth of the receiver to breakthrough half of sampling frequency of AD device without using complex signal and improves the processing bandwidth.

The invention provides an FPGA chip data processing method, a chip, computer equipment and a storage medium, and belongs to the field of radar AD front-end digital processing. The method particularlycomprises the following steps: receiving serial sampling data of a digital-to-analog conversion module by adopting a JESD universal interface, the sampling frequency of the serial sampling data beingnot less than 200MHz; converting the serial sampling data into multiple paths of parallel data through an IP core of the JESD universal interface; respectively carrying out frequency mixing processingon the multiple paths of parallel data by adopting a digital control oscillator to obtain frequency mixing data corresponding to each path of parallel data; and performing filtering processing on each group of frequency mixing data to obtain low-frequency digital-analog sampling data. Through the processing scheme disclosed by the invention, the FPGA chip is simple in design, strong in processingcapacity and easy for engineering practice.