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Deep silicon slot technology

A process technology, a deep silicon technology, is applied in the process field of making deep silicon grooves, which can solve the problems of metal contamination such as chip aluminum, and achieve the effect of no metal contamination and simple and practical process.

Inactive Publication Date: 2003-09-10
无锡微电子科研中心
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the introduction of metals such as aluminum, after DEEP-TRENCH, the chip has serious contamination of metals such as aluminum (using SIMS-secondary ion detection method to measure)

Method used

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  • Deep silicon slot technology
  • Deep silicon slot technology
  • Deep silicon slot technology

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0028] (1), oxidation, oxidize a layer of 100nm thick SiO on the silicon substrate 2 ;

[0029] (2), gluing, in SiO 2 Coat a layer of negative photoresist with a thickness of 1 micron on the layer, and use conventional methods for photolithography and wet etching of SiO 2 , until the silicon substrate window is exposed;

[0030] (3), inject, select BF + Molecular ions are implanted with an energy of 100Kev and a dose of 5E15; where Kev refers to kiloelectron volts;

[0031] (4) For the silicon corrosion tank, use RIE MODE (reactive ion mode) on the dry etching equipment (PHA-520 / 520), and the feeding ratio is CF 4 :O 2 =0.95~0.05 gas, corrosion time is 15 minutes.

[0032] (5), use the conventional wet method to rinse off the remaining SiO 2 , and finally a shallow silicon groove of 1.2-1.35 microns can be obtained.

Embodiment 2

[0034] (1), oxidation, oxidize a layer of 200nm thick SiO on the silicon substrate 2 ;

[0035] (2), gluing, in SiO 2 Coat a layer of negative photoresist with a thickness of 1.2 microns on the layer, and use conventional methods for photolithography and wet etching of SiO 2 , until the silicon substrate window is exposed;

[0036] (3), inject, select BF + Molecular ions are implanted with an energy of 120Kev and a dose of 7E15;

[0037] (4) For the silicon corrosion tank, use RIE MODE (reactive ion mode) on the dry etching equipment (PHA-520 / 520), and the feeding ratio is CF 4 :O 2 =0.95~0.05 gas, corrosion time is 25 minutes.

[0038] (5), use the conventional wet method to rinse off the remaining SiO 2 , and finally a shallow silicon groove of 1.9-2.1 microns can be obtained.

Embodiment 3

[0040] (1), oxidation, oxidize a layer of 500nm thick SiO on the silicon substrate 2 ;

[0041] (2), gluing, in SiO2 Coat a layer of negative photoresist with a thickness of 1.4 microns on the layer, and use conventional methods for photolithography and wet etching of SiO 2 , until the silicon substrate window is exposed;

[0042] (3), inject, select BF + Molecular ions are implanted with an energy of 150Kev and a dose of 4E15;

[0043] (4) For the silicon corrosion tank, use RIE MODE (reactive ion mode) on the dry etching equipment (PHA-520 / 520), and the feeding ratio is CF 4 :O 2 =0.95~0.05 gas, corrosion time is 25 minutes.

[0044] (5), perform implantation again, select phosphorus ions for ion implantation, implant energy of 150Kev and dose of 5E15; then carry out the silicon corrosion tank with the process (4), and the time is 23 minutes.

[0045] (6), use the conventional wet method to rinse off the remaining SiO 2 , and finally a deep silicon groove of 3.9-4.1 m...

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Abstract

A technology for making deep silicon slot includes oxidizing to generate a layer of medium film (hundreds nms-one micron in thickness) on silicon substrate, coating photoresist layer as thick as possible, conventional photoetching, wet corrosion to medium film to expose window on silicon substrate, injecting proper ions, and dry corrosion by introducing CF4 and O2 gas to form deep slot. Its advantages are simple process, high shape of deep silicon slot and no pollution of metals (such as Al).

Description

technical field [0001] The invention relates to integrated circuit technology, in particular to a process for making deep silicon grooves. Background technique [0002] Silicon isolation technology has improved with the improvement of the integration density and function of silicon integrated circuits. DEEP-TRENCH (deep silicon trench) is an important part of Si isolation technology, and there are also filling and planarization. Foreign countries started the research and development of DEEP-TRENCH in the early 1980s. Large companies such as IBM, AT&T, Daimler-BenZ and NEC have invested manpower and material resources in the research and development of Si isolation technology, and have reached a very high level. In Bipolar (bipolar), Bi-CMOS (bipolar CMOS) and IC (integrated circuits) that require high-performance isolation, it has reached more than ten layers of integration, that is, more than ten isolation processes such as DEEP-TRENCH and planarization . This height has...

Claims

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Application Information

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IPC IPC(8): H01L21/76
Inventor 郑宜钧
Owner 无锡微电子科研中心