Storage unit based on 7T1C structure, operation method of storage unit and storage

A technology of storage unit and storage unit array, which is applied in the field of memory and can solve the problems of structural unit stability reduction, consumption, large storage and recovery power consumption, etc.
CN112133347APending Publication Date: 2020-12-25INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Patent Information

Authority / Receiving Office
CN Β· China
Current Assignee / Owner
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
Publication Date
2020-12-25

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Abstract

The invention discloses a storage unit based on a 7T1C structure, an operation method of the storage unit and a memory. The storage unit comprises a 6T structure and a 1T1C structure, and the 6T structure is used for inputting and storing data 1 or 0; and the 1T1C structure is connected with the first storage node of the 6T structure and is used for storing the data 1 or 0 when the 6T structure ispowered off and recovering the data 1 or 0 to the 6T structure when the 6T structure is powered on. By means of the 1T1C structure, under the condition that a read-write circuit of an SRAM in the prior art is not changed, good structural compatibility is kept through simple circuit design, leakage current is prevented, meanwhile, increase of the area size of a storage unit is avoided, the operation speed is higher, and static power consumption is lower.
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Description

technical field

[0001] The invention relates to the technical field of memory, in particular to a memory unit based on a 7T1C structure, an operation method thereof, and a memory. Background technique

[0002] Energy-saving chips (which can be applied to wearable devices and Internet of Things devices, etc.) use Static random access memory (SRAM) for calculation, and non-volatile memory (Non-volatile memory, NVM) for power-off storage, to Reduce standby current. However, this 2-macro (SRAM+NVM) solution is due to high power consumption and slow storage (power off). Therefore, in the case of using low power supply voltage in sleep mode, the SRAM+NVM scheme cannot realize the recovery (start-up) operation caused by frequent power-off and word-by-word serial transmission of data.

[0003] Ferroelectric memory has led to the development of non-volatile logic due to recent advances in NVM devices compatible with Complementary Metal Oxide Semiconductor (CMOS) logic processes, wh...

Claims

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