A copper interconnection structure with a sealing layer and its preparation method

Abstract

The invention discloses a copper interconnection structure with a sealing layer and a preparation method thereof. The copper interconnection structure with the sealing layer comprises: a first layer metal interconnection line (200); a via hole / trench structure formed on the first etch stop layer (201), the first dielectric layer (202 ), the second etch stop layer (203) and the second dielectric layer (204) in the stack, wherein the via hole is located below the trench; the PTCDA film (205) and SiO 2 A thin film (206), wherein the PTCDA thin film (205) covers the sidewall and part of the bottom of the via hole / trench structure, SiO 2 Film (206) covers PTCDA film (205) surface; Copper diffusion barrier layer (208), covers described SiO 2 film (206) and the bottom of the through hole; the second layer of metal interconnection line (209), covering the surface of the copper diffusion barrier layer (208) and completely filling the inside of the through hole / trench structure; copper diffusion covering layer (210 ), covering the upper surface of the above structure. The invention can effectively prevent the copper diffusion barrier layer from penetrating into the porous structure of the low dielectric constant film, avoid the risk of electric leakage, and reduce the probability of pinholes in the growth process of the copper diffusion barrier layer.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a copper interconnection structure with a sealing layer and a preparation method thereof Background technique [0002] With the rapid development of VLSI, the integration level of chips has been continuously improved, and the feature size has been continuously reduced. The multi-layer wiring of metal interconnection leads to the increase of resistance, inter-line capacitance and inter-layer capacitance of metal wires, which increases RC delay time, crosstalk noise and power consumption. These problems have become constraints for the further development of integrated circuits. In order to solve the above problems, on the one hand, Cu metal interconnection wires (resistivity 1.7 μΩ cm) are used instead of Al metal interconnection wires (resistivity 3 μΩ cm) to reduce resistance; on the other hand, low dielectric constant (low k) A dielectric material (such as SiCOH)...

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Problems solved by technology

However, for barrier layers such as TaN and TiN, the steric hindrance effect will occur when the precursor molecules are adsorbed on the substrate surface, which will lead to pinholes easily appearing in the atomic layer deposition process when the barrier layer is very thin, which will reduce the resistance of the barrier layer. The barrier effect of copper diffusion

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