Check patentability & draft patents in minutes with Patsnap Eureka AI!

Memristor-based low-power-consumption pulse convolutional neural network hardware architecture

A technology of convolutional neural network and hardware architecture, which is applied in the field of hardware architecture of low-power pulsed convolutional neural network, can solve problems such as gaps in recognition effects, lack of efficient training algorithms for pulsed convolutional neural networks, and insufficient understanding. To achieve the effect of reducing power consumption

Active Publication Date: 2021-01-05
HEFEI CLT MICROELECTRONICS CO LTD
View PDF6 Cites 24 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Due to the in-depth understanding of the specific learning methods adopted by biological neural networks, the pulsed convolutional neural network currently lacks efficient training algorithms and lacks certain biological basis. Compared with the network, there is still a certain gap
Moreover, the hardware design of the traditional Von Neumann architecture consumes a lot of power and resources

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Memristor-based low-power-consumption pulse convolutional neural network hardware architecture
  • Memristor-based low-power-consumption pulse convolutional neural network hardware architecture
  • Memristor-based low-power-consumption pulse convolutional neural network hardware architecture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0022] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0023] Embodiments of the present invention provide a hardware architecture of a memristor-based low-power pulse convolutional neural network, such as figure 1 As shown, it mainly includes: input buffer (INPUT buffer), memristor control module (RRAM control module), memristor array (RRAM array), sense amplifier (SA) module, and output buffer (OUTPUT buffer device); the input buffer is used to store the image input data, and output the decoding bus ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a memristor-based low-power-consumption pulse convolutional neural network hardware architecture. In the prior art, an existing neural network acceleration hardware architecture adopts a digital circuit multiplier and a digital-to-analog and analog-to-digital converter so as to cause huge hardware power consumption and great area consumption; and a traditional neural network acceleration hardware architecture is difficult to adapt to the requirements that the network scale and the calculation complexity are continuously increased. Compared with the prior art, the technical scheme of the invention adopts a low-power-consumption memristor array to complete simulation multiply-accumulate operation so as to achieve the advantages of being high in operation efficiency and low in power consumption, and adopts an array and a sensitive amplifier to simulate the IF neurons of a pulse convolutional neural network so as to eliminate the digital-to-analog and analog-to-digital converters and save a large amount of hardware area consumption. According to the invention, compared with a traditional convolutional neural network with the defects of large operand and over-high energy consumption, the pulse convolutional neural network has the characteristic of high energy efficiency calculation, so that the memristor-based pulse convolutional neural network hardware architecture provided by the invention has the advantage that the performance is greatly improved.

Description

technical field [0001] The invention relates to the technical field of neural networks, in particular to a hardware architecture of a memristor-based low-power pulse convolutional neural network. Background technique [0002] In recent years, artificial neural networks have become a hot research direction in the field of artificial intelligence. Thanks to the development of big data and high-performance computing hardware, convolutional neural networks have achieved remarkable achievements in the fields of image recognition, object detection and pattern recognition. However, today's computing processors (CPUs) and graphics processing units (GPUs) are based on the traditional von Neumann computing system, which consumes a lot of money in the transfer of data from the memory to the processor. As the amount of data and calculations processed by the neural network is increasing, the traditional von Neumann computing system will consume a very large amount of hardware energy con...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06N3/063G06N3/04G06F13/28
CPCG06F13/28G06N3/065G06N3/045Y02D10/00
Inventor 吴启樵孙文浩蔡元鹏陈松
Owner HEFEI CLT MICROELECTRONICS CO LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More