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Cake type integrated circuit layout method and system for chip

A technology of integrated circuits and layout methods, applied in CAD circuit design, electrical digital data processing, special data processing applications, etc., can solve the problems of increasing the difficulty of chip area reduction, messy and complex chip layout, and affecting the aesthetics of chip layout, etc. , to speed up timing convergence, improve routing rate, and avoid messy and complicated effects

Active Publication Date: 2021-01-12
广芯微电子(苏州)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

According to the layout of traditional integrated circuit layout principles, it will not only greatly increase the difficulty of reducing the area of ​​the chip, but also lead to messy and complex layout of the chip layout, which will affect the overall aesthetics of the chip layout and increase the number of follow-up R&D personnel to organize and integrate. circuit difficulty

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  • Cake type integrated circuit layout method and system for chip
  • Cake type integrated circuit layout method and system for chip
  • Cake type integrated circuit layout method and system for chip

Examples

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no. 1 example

[0044] see Figure 1-3 .

[0045] Such as figure 1 As shown, this embodiment provides a cake-type integrated circuit layout method for chips, at least including the following steps:

[0046] S101. After obtaining the circuit network information netlist provided by the chip front end, perform correlation analysis to obtain a functional correlation table and a logical correlation table between several registers.

[0047]Specifically, for step S101, the netlist netlist provided by the front end is obtained, wherein the netlist netlist is the circuit network information, which includes the cell (unit) information used in the circuit and the connection relationship between them, and also conforms to the Verilog syntax, from The function description of each module in the netlist netlist analyzes the logical relationship of each module (or register), and further determines the correlation between the functions or logic of each module (register), such as the input of each module or ...

no. 2 example

[0068] see Figure 4 .

[0069] Such as Figure 4 As shown, the present embodiment provides a cake-type integrated circuit layout system for chips, including:

[0070] The association analysis module 100 is used to obtain the circuit network information netlist provided by the front end of the chip and perform association analysis to obtain a function association table and a logic association table between several registers.

[0071] Specifically, for the association analysis module 100, the netlist netlist provided by the front end is obtained, wherein the netlist netlist is the circuit network information, which includes the cell (unit) information used in the circuit and the connection relationship between them, and also conforms to the Verilog syntax , analyze the logical relationship of each module (or register) from the functional description of each module in the netlist netlist, and further determine the correlation between functions or logics of each module (registe...

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Abstract

The invention discloses a cake type integrated circuit layout method and system for a chip, and the method comprises the steps: obtaining a circuit network information netlist provided by the front end of the chip, carrying out the correlation analysis, and obtaining a function correlation table and a logic correlation table among a plurality of registers; determining a corresponding required standard cell library according to each functional module used in the chip layout, and sorting the functional modules according to the area of the functional modules; and according to the function association table, the logic association table and the standard cell library, dividing the chip into a plurality of functional areas according to a chip boundary placement principle, and then performing caketype layout of the chip. A unique chip cake type layout method is adopted, the layout flexibility of a large number of functional modules with different sizes during layout is improved, the problem of disorder and complexity during chip layout is avoided, the area required by chip layout is reduced, wiring resources are effectively utilized, the layout pass rate is increased, and the chip layoutcost is reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a cake-style integrated circuit layout method and system for chips. Background technique [0002] IC wiring layout is a crucial part of the digital circuit design process. It has an important impact on whether the timing of the chip is satisfied, the area of ​​the chip, and the final yield of the chip. It will also directly affect the cost of chip tape-out. Especially when the chip reaches a certain scale, due to the need to use more and different sizes of IP modules, macro modules and standard cells for mixed design, in this case, the IP modules and macro modules can be reasonably processed to make the chip more flexible. Satisfying the timing and power supply requirements well while reducing the chip area will become a key technical point in the digital circuit design process. The principle of existing integrated circuits is generally to place IP modules and macro ...

Claims

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Application Information

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IPC IPC(8): G06F30/392G06F115/08
CPCG06F30/392G06F2115/08
Inventor 王锐谭钰鑫李建军王亚波莫军
Owner 广芯微电子(苏州)有限公司