Integrated circuit impedance network model extraction method and system

Abstract

The invention relates to an integrated circuit impedance network model extraction method and system. The method comprises the following steps: acquiring a multilayer integrated circuit layout; performing mesh generation on the multilayer integrated circuit layout to obtain a non-structural triangular mesh for segmenting the multilayer integrated circuit layout; listing a finite element equation set for calculating the potential field of the integrated circuit according to the information of the grid nodes on each triangular grid to obtain a finite element sparse matrix; enabling the finite element sparse matrix to be equivalent to a sparse matrix of an admittance network taking a finite element grid as association; repeatedly performing star triangle transformation on the sparse matrix ofthe admittance network to eliminate internal nodes of a non-port of the sparse matrix to obtain an admittance network of the port; and determining an impedance network model according to the admittance network of the port, and further extracting the impedance network model. The method improves the extraction speed of the impedance network model of the multi-layer super-large-scale integrated circuit.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a method and system for extracting an integrated circuit impedance network model. Background technique [0002] The extraction of multi-layer VLSI impedance network model is an important task in the back-end verification of integrated circuits. The conventional extraction method is to calculate the S-parameter matrix of VLSI using the simplified transmission line method or field-based calculation method, and then based on The S-parameter matrix is ​​converted to an impedance network model. The calculation speed of the transmission line method is fast, but due to the large approximation of the layout of the integrated circuit, the calculation results of the simple and regular layout in the early stage of processing are accurate, but in recent years, the structure has become more and more complex, and the scale ranges from centimeters to centimeters. Nanoscale layouts produce in...

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Problems solved by technology

This method can give very accurate calculation results for the complex layout structure of integrated circuits, but it takes a long time to solve the entire sparse matrix, and after obtaining the field distribution, an additional process is required to calculate the S parameter matrix and convert it into impedance Therefore, this method takes a long time to calculate and the process is complicated, and there will be inevitable errors in the calculation of the S parameter matrix and the conversion of the S parameter matrix into the impedance network model.

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