Scan chain control circuit

Abstract

The invention provides a scan chain control circuit, which is characterized in that a chip test is carried out through an interface on a test circuit board without an external lead at a lead end, andwhen the scan chain control circuit is under the action of a pin shift clock, the scan chain control circuit inputs pin input data to the scan chain test circuit and outputs test data after testing; and when the scan chain control circuit is under the action of a register shift clock signal, the scan chain control circuit inputs register input data to the scan chain test circuit for testing, and outputs test data after the test is completed. According to the invention, test data input / output control of the scan chain test circuit can be realized, the test flexibility is improved, and whether the chip can operate correctly or not can still be tested when the test pins are not easy to expose or poor in contact.

Description

technical field [0001] The invention relates to an integrated circuit chip test circuit, in particular to a control circuit for the scan chain test circuit of the integrated circuit chip. Background technique [0002] With the continuous development of large-scale integrated circuit chip technology, chip integration is getting higher and higher; consequently, chip testing is becoming more and more difficult. The scan chain test circuit has the advantages of high reliability and accurate test, and has been widely used in integrated circuit chip testing, and has become an indispensable component in modern chip design. However, the scan chain test circuit has many test pins, and the existing test method requires external leads during the test, which makes the test difficult. Especially when the chip is packaged on the printed circuit board, too many test pins are not easy to be completely exposed or the chip package causes problems such as poor contact of the test pins, which ...

AI Technical Summary

Problems solved by technology

However, the scan chain test circuit has many test pins, and the existing test method requires external leads, which makes the test difficult

Especially when the chip is packaged on a printed circuit board, too many test pins are not easy to be completely exposed or the chip package causes poor contact of the test pins, which increases the difficulty of testing.

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