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Semiconductor memory device

A technology for memory devices and semiconductors, which is applied in semiconductor devices, electric solid-state devices, electrical components, etc., and can solve problems such as the limitation of integration density of 2D semiconductor devices.

Pending Publication Date: 2021-02-19
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, there are still limitations in increasing the integration density of 2D semiconductor devices since miniaturization of patterns requires expensive equipment

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

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Embodiment Construction

[0021] figure 1 is a block diagram of a semiconductor memory device according to some embodiments of the present disclosure.

[0022] refer to figure 1 , the semiconductor memory device 10 may include a memory cell array 20 and a peripheral circuit 30 .

[0023] The memory cell array 20 may include a plurality of first, second to n th memory cell blocks BLK1, BLK2 to BLKn. Each of the first to nth memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The first to nth memory cell blocks BLK1 to BLKn may be connected to the peripheral circuit 30 via bit lines BL, word lines WL, at least one string selection line SSL, and at least one ground selection line GSL.

[0024] Specifically, the first to nth memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 via word lines WL, string selection lines SSL, and ground selection lines GSL. In addition, the first to nth memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 via bit li...

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PUM

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Abstract

A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logicstructure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyondthe second electrode pad by a second width, which is different from the first width.

Description

technical field [0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a three-dimensional (3D) semiconductor memory device including a vertical channel structure with improved reliability and integration density. Background technique [0002] In order to meet consumer demands for high performance and low price, the integration density of semiconductor devices needs to be increased. Since the integration density is one of the most important factors determining the price of a semiconductor device, there is a need to increase the integration density. The integration density of two-dimensional (2D) or planar semiconductor devices is determined by the area occupied by each unit memory cell, and thus is significantly affected by fine pattern formation techniques. [0003] However, since the miniaturization of patterns requires expensive equipment, there is still a limit in increasing the integration density of 2D semiconductor devices. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11578H01L27/11573
CPCH10B43/40H10B43/20H10B43/10H10B43/50H10B43/27H01L29/792H10B43/35
Inventor 李海旻姜信焕韩智勋
Owner SAMSUNG ELECTRONICS CO LTD
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