SCE-MI protocol bridge and simulation system

Abstract

The invention discloses an SCEMI protocol bridge and system, and the SCEMI protocol bridge comprises a data conversion module, a parallel bus, a plurality of channel data receiving and transmitting control modules, a plurality of data FIFO channels, a protocol drive module, a plurality of channel data blocks, a plurality of data receiving and transmitting modules, and a plurality of channel data queues, and the protocol driving module is connected with the data conversion module. The SCEMI protocol bridge has the advantages of being high in bandwidth, small in delay and capable of dynamicallyconfiguring the number of ports.

Description

technical field [0001] The invention relates to the field of chip design, in particular to an SCE-MI protocol bridge and a simulation system. Background technique [0002] As the scale of the chip is getting larger and larger, the time spent on chip verification is getting longer and longer, even exceeding 70% of the time of chip development. One of the important reasons is that the simulation speed is too slow. It takes more than a month to simulate a large-scale chip using the fastest server. Therefore, some methods are urgently needed to improve the simulation speed. One method is to use a hardware-software co-simulation accelerator (Emulator), which runs the chip code on the hardware and the simulation code runs on the server. The current standard for communication between software and hardware is the SCE-MI protocol, but this protocol only defines the user interface, and the specific implementation method is not explained, which leads to difficulties in communication b...

AI Technical Summary

Problems solved by technology

The current standard for communication between software and hardware is the SCE-MI protocol, but this protocol only defines the user interface, and the specific implementation method is not explained, resulting in difficulties in communication between software and hardware co-simulation

[0003] In order to solve the above technical problems, in the Chinese patent CN201610520860.7, a routing ID is designed to achieve routing, and all data transmission is through the physical channel PCIe or Ethernet Since the routing information will occupy more bus bandwidth, the effective bandwidth will be smaller when the data packet is relatively small. At the same time, because the processing of routing information will consume a certain clock cycle, the delay will be greater. It can be seen that the scheme The delay is large and the bandwidth is small; at the same time, the data transmission of this solution is actively read or written by the software to the hardware. Since the CPU needs to spend a lot of machine cycles to process a piece of data and the CPU needs to process many tasks, the transmission speed will be relatively slow.

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