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Clock frequency detection circuit, clock control circuit and clock frequency detection method

A clock frequency and detection circuit technology, applied in the field of microelectronics, can solve the problems of high test cost and high test design complexity, and achieve the effect of reducing complexity, equipment and time costs

Pending Publication Date: 2021-04-27
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Embodiments of the present invention provide a clock frequency detection circuit, a clock control circuit, and a clock frequency detection method to at least solve the problem of high test cost and high complexity of test design in the process of detecting the clock network frequency in a chip in the related art The problem

Method used

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  • Clock frequency detection circuit, clock control circuit and clock frequency detection method
  • Clock frequency detection circuit, clock control circuit and clock frequency detection method
  • Clock frequency detection circuit, clock control circuit and clock frequency detection method

Examples

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Embodiment 1

[0042] This embodiment provides a clock frequency detection circuit, figure 1 It is a functional schematic diagram (1) of a clock frequency detection circuit provided according to an embodiment of the present invention, as figure 1 As shown, the clock frequency detection circuit in this embodiment includes:

[0043] The measurement module 102 includes a first clock counter 1022, the first clock counter is configured to count the first clock signal in the first cycle, so as to obtain the count value of the first clock signal in the first cycle; wherein, the first clock The signal is a clock signal input by the clock to be tested;

[0044] The comparison module 104 is configured to compare the calculated value with the expected value of the first clock signal in the first period to obtain a comparison result;

[0045]The control chain module 106 is configured to obtain an expected value according to the chain test vector, and send the expected value to the comparison module 10...

specific Embodiment 1

[0073] Figure 5 It is a schematic circuit diagram of a clock frequency detection circuit provided according to a specific embodiment of the present invention, combined below Figure 5 The input signal, output signal and specific configuration of the clock frequency detection circuit in this specific embodiment will be described.

[0074] The input signal of the clock frequency detection circuit in this specific embodiment includes:

[0075] 1) SI: input control signal of the scan chain;

[0076] 2) PLL_CLK: a high-speed clock signal, the PLL_CLK comes from the internal phase-locked loop output of the chip, and the PLL_CLK is the first clock signal in the above-mentioned embodiment. In this specific embodiment, the above-mentioned PLL_CLK is the clock signal for frequency detection ;

[0077] 3) ATE_CLK: a low-speed clock signal, the ATE_CLK is directly input by the peripheral ATE testing machine, the ATE_CLK is the second clock signal in the above embodiment, and the inher...

Embodiment 2

[0089] This embodiment provides a clock control circuit, including the clock frequency detection circuit described in Embodiment 1, Figure 6 It is a functional schematic diagram (1) of a clock control circuit provided according to an embodiment of the present invention, such as Figure 6 As shown, the clock control circuit in this embodiment includes:

[0090] The first input module 202 is configured to input a first clock signal;

[0091] The control module 204 is configured to control the first clock signal, and obtain a chain test vector, and send the chain test vector to the control chain module in the clock frequency detection circuit.

[0092] It should be further explained that the clock control circuit in this embodiment may be an OCC circuit, or other circuits for realizing relevant clock control functions, which is not limited in the present invention.

[0093] It should be further explained that the control module in this embodiment is the module corresponding to...

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Abstract

The invention provides a clock frequency detection circuit, a clock control circuit and a clock frequency detection method. The clock control circuit comprises: a measurement module comprising a first clock counter, wherein the first clock counter is configured to obtain a counting value of a first clock signal in a first period; a comparison module configured to compare the calculated value with an expected value of the first clock signal in a first period so as to obtain a comparison result; and a control chain module configured to obtain an expected value according to the string chain test vector, send the expected value to the comparison module, obtain a comparison result according to the string chain test vector, and perform frequency detection on the to-be-detected clock according to the comparison result. According to the invention, the problems of over-high test cost and relatively high test design complexity in the process of detecting the clock network frequency in the chip in the related technology are solved, so that the effect of reducing the equipment and time cost in the process of detecting the clock network frequency in the chip is achieved.

Description

technical field [0001] The invention relates to the field of microelectronics, in particular to a clock frequency detection circuit, a clock control circuit and a clock frequency detection method. Background technique [0002] At present, the scale and complexity of digital chip design are getting larger and higher. Therefore, the requirements and challenges for Design For Test (DFT) in the chip design process are also getting higher and higher: at present, DFT needs to be improved While testing the quality, reduce the test time as much as possible, reduce the resource requirements of test pins, and reduce the complexity of test circuit design and integration. [0003] There are many clock generation or processing modules on the internal clock network of the chip, such as phase-locked loops, frequency dividers, clock switching circuits, etc., traditional serial chain (SCAN), memory built-in test (Memory Built In Self Test, MBIST) The DFT test method cannot directly cover th...

Claims

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Application Information

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IPC IPC(8): G01R31/317
CPCG01R31/31727
Inventor 彭敏强
Owner SANECHIPS TECH CO LTD