DAC circuit with controllable differential output common-mode voltage in SAR-ADC and control method thereof

Abstract

The invention provides a DAC circuit with controllable differential output common-mode voltage in an SAR-ADC, a control method of the DAC circuit and a DAC capacitor array. A DAC capacitor array and a DAC common-mode voltage regulation module are combined to form the DAC circuit, sampling and holding of the SAR-ADC are realized in cooperation with logic control, and a common-mode voltage is prevented from being generated by using a divider resistor with continuous static power consumption or current mirror bias. The logic control of the sampling holding stage is as follows: an upper polar plate of a DAC capacitor array and upper and lower polar plates of a DAC common-mode voltage regulation module capacitor are connected with a reference high voltage, and a lower polar plate of the DAC capacitor array is respectively connected with an input signal for sampling; after the sampling is finished, the upper polar plate of the DAC capacitor array is disconnected from the reference high voltage, the lower polar plate of the DAC capacitor array is disconnected from the sampling input signal, the lower polar plate of the capacitor in the DAC common-mode voltage regulation module is switched to be connected with the reference low voltage, and the maintenance of the sampling signal and the establishment of the DAC output common-mode voltage are finished.

Description

technical field [0001] The invention relates to the field of circuit control, in particular to a DAC circuit used in a SAR-ADC with controllable differential output common-mode voltage and a control method thereof. Background technique [0002] SAR-ADC is an analog-to-digital converter with high speed, high precision and small power consumption area. The existing differential input 12Bit capacitive lower-level board sampling capacitor array (DAC) module and comparator (CMP) module architecture of SAR-ADC is as follows: figure 1 shown. Its working process includes two stages: the first is the sampling stage, the two upper plates are connected to the common mode voltage (Vcm), and the two lower plates are respectively connected to the differential input signals Vip and Vin, and the DAC capacitor array is used for sampling; after the sampling is completed, The two upper plates are disconnected from Vcm, and the two lower plates are disconnected from the input signal to comple...

AI Technical Summary

Problems solved by technology

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a DAC circuit and a control method for controlling the differential output common-mode voltage in the SAR-ADC, which are used to solve the problems existing in the SAR-ADC architecture in the prior art. The problem of high power consumption of the common-mode voltage generation circuit and how to meet the needs of low-voltage technology

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