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Elmore delay time (EDT)-based resistance model

A technology of point-to-point resistors and capacitors, which can be used in database models, CAD circuit design, electrical digital data processing, etc., and can solve problems such as inaccurate resistor models

Active Publication Date: 2021-05-07
SYNOPSYS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Resistive models using conventional 1D current flow are not accurate for these complex structures

Method used

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  • Elmore delay time (EDT)-based resistance model
  • Elmore delay time (EDT)-based resistance model
  • Elmore delay time (EDT)-based resistance model

Examples

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Embodiment Construction

[0036] The following discussion is presented to enable any person skilled in the art to make and use the disclosed technology, and is presented in the context of a particular application and its requirements. Various modifications to the disclosed implementations will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other implementations without departing from the spirit and scope of the disclosed technology and apply. Thus, the disclosed technology is not intended to be limited to the implementations shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

[0037] introduction

[0038] We propose a novel 2D / 3D field solver that generates resistor values ​​that account for both 2D transistor topology and 3D transistor topology. The field solver is based on Elmore delay time (EDT), which is consistent with the Rg / 3 approach. Regarding EDT, the Elmore delay at a nod...

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Abstract

We disclose an integrated circuit design tool for modeling resistance of a terminal of a transistor such as a gate, a source, a drain, and a via. A structure of the terminal is specified in a data structure in memory using a three-dimensional (3D) coordinate system. For each of a plurality of volume elements in the specified structure, an Elmore delay time (EDT) is determined. For those volume elements in the plurality of volume elements that are located on a surface of the gate terminal which faces the channel region, an average EDT (aEDT) is determined based on the EDT. Point-to-point resistance values of the terminal are generated as a function of the aEDT and a capacitance of the terminal.

Description

[0001] priority application [0002] This application claims the benefit of U.S. Nonprovisional Patent Application No. 16 / 568,984, filed September 12, 2019, which claims U.S. Provisional Patent Application No. 62 / 731,147, filed September 14, 2018 and filed September 19, 2018 benefit of U.S. Provisional Patent Application No. 62 / 733,317 filed on . All of the above applications are incorporated herein by reference. technical field [0003] The disclosed technology relates to the modeling of integrated circuit devices in computer aided design (CAD) systems and electronic design automation (EDA) systems, and more particularly, to the modeling and simulation of conductors in integrated circuits (ICs). Background technique [0004] An integrated circuit (IC) is a group of electronic circuits integrating a large number of semiconductor transistors into a small chip. State-of-the-art integrated circuits include microprocessors, memory chips, programmable logic sensors, power mana...

Claims

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Application Information

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IPC IPC(8): G06F30/39G06F30/3312G06F30/398G06F30/367G06F16/28G06F119/12
CPCG06F30/367G06F2119/12G06F30/31G06F30/3312G06F30/398G06F16/283G06F30/39
Inventor R·B·艾弗森
Owner SYNOPSYS INC