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Three-dimensional memory, circuit chip and preparation method thereof

A technology of circuit chips and MOS devices, which is applied in the direction of circuits, electrical components, semiconductor devices, etc., can solve the problem that circuit chips cannot be further reduced in size, and achieve the effect of improving body effect, high input impedance, and reducing size

Active Publication Date: 2021-05-11
YANGTZE MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a three-dimensional memory, a circuit chip and a preparation method thereof, so as to solve the technical problem that the size of the circuit chip cannot be further reduced

Method used

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  • Three-dimensional memory, circuit chip and preparation method thereof
  • Three-dimensional memory, circuit chip and preparation method thereof
  • Three-dimensional memory, circuit chip and preparation method thereof

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Embodiment Construction

[0028]Next, the technical solutions in the embodiments of the present invention will be apparent from the embodiment of the present invention, and it is clearly described, and it is understood that the described embodiments are merely embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, those of ordinary skill in the art will belong to the scope of the present invention without all other embodiments obtained without creative labor.

[0029]The preparation method of the conventional circuit chip is briefly described before describing the specific embodiment of the present invention.

[0030]Seefigure 1 The preparation method of the conventional circuit chip is: forming the MOS device 50 on the substrate 10, and the adjacent MOS device 50 is interleaned by the shallow trench isolation structure (STI) 20, shallow in the X direction and the Y direction. The p-type field implant is injected into the trench isolation structure (STI...

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Abstract

The invention provides a three-dimensional memory, a circuit chip and a preparation method thereof. The preparation method of the circuit chip comprises the following steps: providing a substrate; forming a plurality of shallow trench isolation structures which are arranged at intervals in the substrate, arranging an active region between the adjacent shallow trench isolation structures; and forming an auxiliary grid electrode in the shallow trench isolation structure, forming an MOS device in the active region. The MOS device comprises a grid electrode structure, a source electrode and a drain electrode, the source electrode and the drain electrode are located on the two sides of the grid electrode structure, and the auxiliary grid electrode is located between the source electrode of one MOS device and the drain electrode of the other MOS device in the adjacent MOS devices. The size of the circuit chip is small.

Description

Technical field[0001]The present invention relates to the technical field of semiconductor device, and more particularly to a three-dimensional memory, a circuit chip, and a preparation method thereof.Background technique[0002]In the three-dimensional memory, the circuit chip size restricts the spacing between the high voltage MOS devices in the X and Y directions in the word line decoding transmission transistor circuit. During the unit programming operation, the transmission transistor needs to transmit a high voltage of 25V of the source / drain region at a gate voltage of 29V, and the voltage difference between adjacent high voltage MOS devices is about 25V. Under the prior art, the p-type field implant is formed between the X direction and the Y direction to suppress the throughput, which makes the spacing between the high voltage MOS device cannot continue to shrink, and the circuit chip cannot be Further size.Inventive content[0003]It is an object of the present invention to ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11521H01L27/11551H01L27/11568H01L27/11578H10B41/30H10B41/20H10B43/20H10B43/30
CPCH10B41/20H10B43/30H10B43/20H10B41/30
Inventor 陈亮刘威王言虹
Owner YANGTZE MEMORY TECH CO LTD
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