Chip cross section identification mark and manufacturing method thereof

Abstract

The invention discloses a chip cross section identification mark and a manufacturing method thereof, the chip cross section identification mark comprises a plurality of metal layers and metal through hole layers arranged among the metal layers, and all the metal layers and the metal through hole layers jointly form the shape of the whole identification mark; and the identification mark is inserted into the position where the original function and performance of the chip are not affected in the cross section view of the chip to be inserted with the identification mark. The method comprises the steps of: firstly, determining a preset identification mark; determining the insertion position of a preset identification mark in combination with each cross-sectional view of the chip; and combining each layer of the chip with each layer of the preset identification mark in combination with the determined insertion position, storing the combined layers in a GDSII file, and delivering the GDSII file to a process plant to produce the chip containing the identification mark. The mark has hiding performance, and under the condition that chip design ownership is dispute, ownership affirmation can be carried out; the mark and the original circuit are fused together, any erasing operation may cause the logic failure of the circuit, and the mark cannot be erased.

Description

technical field [0001] The invention relates to a chip cross-section identification mark and a manufacturing method thereof, belonging to the technical field of chip marks. Background technique [0002] Generally speaking, we often complete the physical design of the chip through the top view of the chip, and physically divide the chip into different layers. If there is a logical relationship between the layers, the circuit connection is completed through through holes. The bottom layers of the chip are logic devices, such as figure 1 The shown NAND gate, etc.; while other layers of the chip complete the circuit connection to these logic devices to realize their functions (such as figure 2 As shown, the circuit connection is realized through multiple layers, and in the design tool, different layers are represented by different colors). If viewed from the cross-section of the chip, it will appear as follows image 3 Schematic shown. [0003] At present, after the chip de...

AI Technical Summary

Problems solved by technology

[0006] In view of the problems existing in the above-mentioned prior art, the present invention provides a chip cross-section identification mark and its manufacturing method, which can solve the problem that the original mark does not have concealment, and can carry out ownership identification in the case of disputes over the ownership of the chip design ;Integrating the mark with the original circuit, any erasing operation may invalidate the logic of the circuit, and the mark cannot be erased

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