Standard cell delay model construction method based on logarithm expansion partial normal distribution

Abstract

The invention discloses and protects a standard cell delay model construction method based on logarithmic expansion partial normal distribution, and the method comprises the steps: setting a plurality of working condition scenes for each standard cell, taking the cell delay distribution data about process fluctuation obtained through SPICE simulation as training data under different working conditions, and fitting the logarithm expansion partial normal distribution model by using a maximum likelihood estimation method to obtain a model coefficient; regarding the logarithm expansion partial normal distribution model coefficient as a parameter related to a working condition, establishing a quadratic model, fitting a multivariate function of the logarithm expansion partial normal distribution model coefficient about the working condition through a nonlinear regression method, and finally achieving the standard unit delay model based on logarithm expansion partial normal distribution.

Description

technical field [0001] The invention belongs to the field of integrated circuit design automation (EDA), in particular to a method for constructing a standard unit delay model based on logarithmically extended partial normal distribution. Background technique [0002] Timing analysis is a very important link in the design of large-scale integrated circuits. It can verify the correctness of the design in timing and determine whether the design can run at the required operating frequency, thereby ensuring the function and stability of the chip. As the integrated circuit manufacturing process enters the deep sub-micron era, at TSMC16nm or more advanced process nodes, the standard cell delay becomes more sensitive to changes in process fluctuation parameters. Due to the influence of various uncertain factors such as the accuracy of the equipment itself, the manufacturing environment, and human error, the actual manufactured chip parameters and the theoretically designed chip par...

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Problems solved by technology

[0004] However, under the working condition of near-threshold low voltage, the impact of process fluctuations on cell delay is intensified, and the distribution of cell delay appears asymmetric and tailing, showing non-Gaussian distribution characteristics

The mean and standard deviation determine the size and range of the statistical distribution, and cannot change the symmetry and tailing of the distribution

Therefore, using a Gaussian model to fit the delay distribution of a standard cell under near-threshold low-voltage operating conditions will bring large errors, which cannot meet the design requirements

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