Dual-channel router in network-on-chip and routing method thereof

Abstract

The invention discloses a dual-channel router in a network on chip and a routing method of the dual-channel router, and the router is additionally provided with additional input and output channels in the east, south, west and north directions so as to improve the packet forwarding efficiency; a virtual channel distribution module is removed, and the implementation overhead and the design complexity of the router are reduced; a forward route and a low-load bypass are added to reduce the stage number of the assembly line; and a cascade crossbar switch design is adopted, so that the problem of resource competition between groups is relieved. Compared with the prior art, the method has the advantages that the area and the power consumption overhead are relatively low, the quantity of pipeline stages is efficiently reduced, the resource contention between groups is relieved, the average group delay is reduced, the highest clock frequency of the router and the network throughput are improved, and the network performance is greatly improved.

Description

technical field [0001] The invention belongs to the application technical field of integrated circuit chip design, in particular to a router with dual-input and dual-output channels and a routing method that can be used in a 2D Mesh on-chip network. Background technique [0002] Since the 1950s, with the rapid development of semiconductor technology and integrated circuit technology, the integration of System-on-Chip (SoC) has become higher and higher, and hundreds of microprocessors such as microprocessors can often be integrated on a single chip. Intellectual property cores (Intellectual Property Cores, IP cores) of memory, I / O interface. For example, Intel and AMD have increased the number of cores of commercial chips to a scale of 64 cores. As system performance requirements become higher and higher, the interconnection architecture between IP cores must be able to provide services with low latency and high throughput, and have good scalability. Network-on-Chip (NoC) i...

AI Technical Summary

Problems solved by technology

However, only the packet that wins the arbitration in both phases can enter the ST phase, otherwise the current packet must re-execute the two phases in the next cycle, so this design can achieve lower latency only in lightly loaded networks , a higher network load will greatly reduce the probability of winning the group arbitration, which not only fails to reduce the pipeline stage, but also wastes energy in vain

There is also a router architecture design for express virtual channels (Express virtual channels, EVCs), which bypasses the entire pipeline by allowing packets to skip the arbitration in the pipeline to achieve lower latency and higher throughput, but the design It can only bypass up to three-quarters of the router pipeline in the transmission path. In addition, the design requires different design of bypass nodes and source and sink nodes, thus introducing higher overhead and design complexity

There is also a bidirectional router architecture design that supports dynamic channel direction. This design replaces the original unidirectional input and output channels with bidirectional channels, and dynamically adjusts the channel direction through its channel direction control (Channel direction control, CDC) protocol to increase the distance between routers. Inter-bandwidth, thereby improving the throughput of the entire network, but this design introduces a larger crossbar switch and a more complex crossbar distribution module, which consumes more area and energy

The above existing designs share the following problems: First, the virtual channel allocation is a key delay stage of the pipeline. Due to the complexity of this stage, it is difficult for the router to increase its maximum clock frequency, thereby limiting the performance improvement of the entire network; The improvement of the need to add more complex arbitration logic or a larger crossbar switch, at the expense of the area and power consumption overhead and design complexity of the router; the third is that the competition for the same resource between multiple groups in the router cannot be solved Effective mitigation, the way of prioritizing packets or link directions requires additional control strategies or protocols, and inefficient control strategies or protocols are not enough to significantly improve performance

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