3D stacked and back exported fan-out type packaging structure and manufacturing method thereof

Abstract

The invention discloses a 3D stacked and back exported fan-out type packaging structure and a manufacturing method thereof. The fan-out type packaging structure comprises a carrier plate (wafer), a chip, a plastic packaging layer, a first rewiring layer, a first dielectric layer, a second rewiring layer and a second dielectric layer. According to the fan-out type packaging structure, double-sided fan-out is realized, the packaging cost can be effectively reduced, and the application range of the structure is widened; the structure mainly depends on the design of the substrate to realize interconnection and intercommunication of the front surface and the back surface of the chip instead of TSV through holes, so that the process difficulty can be effectively reduced, and processing and production can be realized by using general equipment; besides, the fan-out type packaging structure can shorten the connection distance, has great advantages in the aspects of product performance, especially electrical performance and signal transmission, and is smaller in loss, higher in efficiency and shorter in response time.

Description

technical field [0001] The present invention relates to semiconductor wafer packaging technology, more specifically, to a 3D stacked fan-out package structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, semiconductor devices are becoming more and more complex, and the volume of semiconductor devices is also becoming smaller and smaller. In addition, semiconductor devices are required to have more functions and faster processing speeds. In order to support the increased functions, the semiconductor package including these components has a large number of contact pads for external electrical connection, such as for input or output, these contact pads will greatly increase the surface area of ​​the semiconductor package, and even occupy the semiconductor half of the package surface area. [0003] The traditional wafer-level packaging technology uses fan-in technology (Fan-in), which requires that the chip...

AI Technical Summary

Problems solved by technology

This kind of 2.5D / 3D wafer-level packaging has limited integration, and it is difficult to carry out wafer-level testing in TSV technology. It is difficult to guarantee the yield rate of chips, and the final packaging yield is low, which in turn increases the cost of packaging.

In addition, in the case of stacked package layers, it is difficult to reduce the volume of the stacked package due to the large number of intermediate layers, and this type of package will also increase the volume of the package due to the problem of assembly accuracy.

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