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High-performance synchronous overmodulation algorithm for diode-clamped three-level inverter

A three-level inverter and diode clamping technology, which is applied in the direction of AC motor control, electrical components, control systems, etc., can solve problems such as unfavorable engineering applications, poor harmonic performance of inverters, and complex algorithms, and achieve improvement Effects of current harmonic performance, reduction of switching frequency and switching loss, and simplified calculation process

Active Publication Date: 2021-08-17
希望森兰科技股份有限公司
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Problems solved by technology

Among them, the single-mode algorithm engineering implementation is relatively simple, but the harmonic performance of the inverter output is poor
The dual-mode algorithm can improve the inverter output harmonics, but the algorithm is very complicated, which is not conducive to engineering applications

Method used

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  • High-performance synchronous overmodulation algorithm for diode-clamped three-level inverter
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  • High-performance synchronous overmodulation algorithm for diode-clamped three-level inverter

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Embodiment Construction

[0046] The present invention will be described in further detail below in conjunction with accompanying drawing and specific embodiment, so that those skilled in the art understand the present invention, but should be clear, the present invention is not limited to the scope of specific embodiment, to those of ordinary skill in the art In other words, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concept of the present invention are included in the protection list.

[0047] The specific implementation steps are as follows.

[0048] A high-performance synchronous overmodulation algorithm for a diode-clamped three-level inverter, comprising the following steps:

[0049] Step 1: Establish a mathematical model of a diode-clamped three-level inverter. Diode-clamped three-level inverter topology such as figure 1 shown. In the d...

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Abstract

The invention discloses a high-performance synchronous overmodulation algorithm for a diode-clamped three-level inverter, and the algorithm employs a four-segment vector synthesis mode, and reduces the switching frequency of the inverter to a half of the switching frequency of a conventional seven-segment vector synthesis mode. In an overmodulation region, volt-second balance is realized by innovatively utilizing an area equivalence principle, and basic voltage vector action time enabling the fifth harmonic content and the seventh harmonic content of output voltage to be minimum is calculated according to Fourier analysis, so that low-frequency current harmonics and torque ripples caused by low switching frequency are suppressed. The algorithm solves the problems that a traditional algorithm is high in switching frequency and large in current and torque harmonic waves, and has the advantages of being simple in algorithm and high in applicability.

Description

technical field [0001] The invention relates to the modulation field of a diode-clamped three-level inverter in the field of power electronics and electric transmission, in particular to a high-performance diode-clamped three-level inverter with low switching frequency, torque ripple and current harmonics Synchronous overmodulation algorithm. Background technique [0002] Compared with traditional two-level inverters, diode-clamped three-level inverters have lower tube voltage drop and lower output harmonics at the same switching frequency. Therefore, diode-clamped three-level inverters have been widely used in medium-voltage and high-power motor drive applications. Currently, there are two common modulation algorithms for diode-clamped three-level inverters: space voltage vector modulation and carrier pulse width modulation. These two algorithms have been widely used and popularized in the industry because of their good harmonic performance and relatively simple algorithm...

Claims

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Application Information

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IPC IPC(8): H02M7/483H02M7/5387H02M1/12H02P27/12G06F17/11
CPCG06F17/11H02M1/12H02M7/483H02M7/53875H02P27/12
Inventor 张树林宋玉明任光法张正松
Owner 希望森兰科技股份有限公司
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