Dummy gate planarization method in gate-last process

Abstract

The invention discloses a dummy gate planarization method in a gate-last process. The method comprises the following steps: 1, forming a dummy gate material layer on the surface of a semiconductor substrate, carrying out photoetching definition, and simultaneously defining a forming region of a dummy gate and a forming region of a trench in a gate; 2, etching the dummy gate material layer, and forming a dummy gate and a gate inner groove at the same time; 3, forming a grinding barrier layer on the side surface of the groove in the gate; 4, forming a zeroth interlayer film; and 5, performing chemical mechanical polishing to enable the zeroth interlayer film to be flush with the surfaces of the dummy gates and expose the surfaces of the dummy gates, adjusting the polishing load of each dummy gate by polishing the barrier layer and combining with the layout of the grooves in the gates, and enabling the heights of the dummy gates to be uniform after the chemical mechanical polishing is completed. According to the invention, the grinding load of the dummy gates with different sizes can be uniform, the height uniformity in the dummy gates and the height uniformity of the dummy gates with different sizes can be improved, the performance of the device can be stable, and the reliability of the device can be improved.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a dummy gate planarization method in a gate-last process. Background technique [0002] With the continuous reduction of device size, for high-voltage (HV) COMS devices with process nodes below 32nm, especially below 28nm, the high dielectric constant (HK) gate dielectric-metal gate (MG) or HKMG process has become a development direction. Currently, there are Gate-first and Gate-last HKMG technologies. For Gate-first technology, since the metal gate needs to undergo multiple high-temperature processes, it will seriously affect the performance and reliability of the device. In contrast, the Gate-last technology can effectively avoid high-temperature processes and effectively ensure device performance and reliability, but the flatness of the pseudo-gate structure has become a key step for the uniformity of the metal gate height. [0003] In the gate...

AI Technical Summary

Problems solved by technology

[0006] The first aspect is to improve the selectivity of the CMP slurry, the hardness of the polishing pad and increase the pressure to optimize the loading of patterns (Pattern) of different sizes by CMP, but it will inevitably cause scratches (Scratch) and particles (Defects such as Particle)

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