Method for forming semiconductor structure

A semiconductor and gate structure technology, which is applied in the field of semiconductor structure formation, can solve the problems of poor semiconductor structure performance and reliability, and achieve the effect of increasing the area, increasing the injection angle, and reducing the length.

Pending Publication Date: 2021-09-28
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

[0004] However, the performance and reliability of semiconductor structures form

Method used

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  • Method for forming semiconductor structure
  • Method for forming semiconductor structure
  • Method for forming semiconductor structure

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Experimental program
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Embodiment Construction

[0033] As mentioned in the background art, the performance and reliability of the semiconductor structure formed to overcome the short channel effect of the transistor in the prior art are poor. The following will describe in detail with reference to the accompanying drawings.

[0034] Figure 1 to Figure 3 It is a structural schematic diagram of each step in the formation process of a semiconductor structure.

[0035] Please refer to figure 1 , providing a substrate 100 with several fins 101 separated from each other on the substrate 100; forming a gate structure 102 on the substrate 100, the gate structure 102 straddling the fins 101, and the The gate structure 102 covers part of the top and sidewall surfaces of the fin 101 .

[0036] Please refer to figure 2 , forming source and drain openings 103 in the fins on both sides of the gate structure 102; performing first ion implantation on the source and drain openings 103, forming in the substrate 100 on the side walls an...

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Abstract

A method for forming a semiconductor structure comprises the following steps: providing a substrate; forming a gate structure, a first side wall and a second side wall on the substrate; forming a source-drain opening in the substrate by taking the first side wall and the second side wall as masks; removing the second side wall; carrying out ion implantation on the source-drain opening, and forming a suppression layer in the substrate on the side wall and the bottom of the source-drain opening, wherein first ions are doped in the suppression layer; and forming a source-drain doping layer in the source-drain opening. The second side wall and the source-drain opening are firstly formed, and the second side wall is removed after the source-drain opening is formed, so that the injection angle during first ion injection is increased, more injected first ions are diffused into the substrate corresponding to the side wall of the source-drain opening, the surrounding area of the suppression layer is increased, and in the subsequent activation annealing treatment, the second ions in the source-drain doping layer can be diffused in a large area range, so the area of the finally formed source-drain doping region is increased, and the performance of the finally formed semiconductor structure is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. Transistors, as the most basic semiconductor devices, are being widely used at present. The control ability of traditional planar transistors on channel current is weakened, resulting in short channel effect and leakage current, which ultimately affects the electrical performance of semiconductor devices. [0003] In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the fin field effect transistor includes : the fin and the dielectric layer located on the surf...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/265H01L29/78
CPCH01L21/26513H01L29/66795H01L29/785
Inventor 金吉松亚伯拉罕·庾
Owner SEMICON MFG INT (SHANGHAI) CORP
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