Manufacturing method of semiconductor structure

Abstract

Embodiments of the present invention provide a method for fabricating a semiconductor structure. The manufacturing method of the semiconductor structure includes: providing a substrate; forming a plurality of mutually discrete first mask layers on the substrate; forming a plurality of sidewall layers, each sidewall layer surrounding a first mask layer, and each sidewall layer and the The other sidewall layers closest to each other are connected, and the sidewalls of the plurality of connected sidewall layers facing away from the first mask layer form an initial first through hole, and the initial first through hole has a chamfer; the first mask layer is removed, Each sidewall layer surrounds a second through hole; after removing the first mask layer, a repair layer is formed, and the repair layer is located on the sidewall of the sidewall layer facing away from the second through hole; the repair layer is also filled in the initial first through hole to form a first through hole; and the substrate is etched along the first through hole and the second through hole to form a capacitor hole in the substrate. The embodiments of the present invention can improve the yield of the semiconductor structure.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular to a method for manufacturing a semiconductor structure. Background technique [0002] Dynamic Random Access Memory (DRAM for short) is a semiconductor memory widely used in computer systems. Its main function principle is to use the amount of charge stored in a capacitor to represent a binary bit (bit). [0003] At present, self-aligned double patterning (SADP) is usually used to form capacitors. It generally needs to form two layers of mask patterns, both of which include trench structures arranged at intervals, and viewed from a top view, the two layers of mask patterns are oblique to each other, and then the two layers of mask patterns are transferred. to the target mask layer to define the capacitor hole pattern and prepare the capacitor. However, due to the load effect during etching, such SADP process is prone to problems such as different capacitor sizes, different hei...

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Problems solved by technology

It generally needs to form two layers of mask patterns, both layers of mask patterns include groove structures arranged at intervals, and from a top view, the two layers of mask patterns are oblique to each other, and then the two layers of mask patterns are transferred To the target mask layer to define the capacitor hole pattern and prepare the capacitor. However, due to the load effect in etching, such SADP process is likely to cause problems such as different capacitor sizes, different heights, insufficient etching, and reduced capacitor storage power. thereby reducing the yield of the semiconductor structure

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