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PIP capacitor and forming method

A capacitor and pseudo-gate structure technology, applied in capacitors, circuits, electrical components, etc., can solve the problems of reducing the capacitance value of PIP capacitors, reducing the area, affecting the demand, etc., to increase the capacitance value, increase the cost, and increase the relative area effect

Pending Publication Date: 2021-11-19
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the size of electronic products decreases, the size of the PIP capacitor also needs to be reduced, resulting in a reduction in the area of ​​the upper plate and the lower plate of the PIP capacitor, and finally the capacitance value of the manufactured PIP capacitor is reduced.
Affects the demand for high-capacitance PIP capacitors in electronic devices

Method used

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Embodiment Construction

[0035] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0036] Please refer to figure 2 , the invention provides a method for forming a PIP capacitor, comprising:

[0037] S11: providing a substrate, the substrate including a CELL region and a PIP region;

[0038] S12: forming a shallow trench isolation structure in the substrate of the PIP region;

[0039] S13: While using a gate structure photomask to form multiple spaced gate structures on the substrate of the CELL region, use a gate structure photomask to form multiple spaced gate structures on the shallow tre...

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Abstract

The invention provides a PIP capacitor and a forming method thereof. The method comprises the steps of providing a substrate which comprises a CELL region and a PIP region, forming a shallow trench isolation structure in the substrate of the PIP region, forming a plurality of spaced gate structures on the substrate of the CELL region by using a photomask of the gate structures, forming a plurality of spaced pseudo gate structures on the shallow trench isolation structure by using a photomask of the gate structures, exposing the surfaces of the shallow trench isolation structure among the plurality of pseudo gate structures, and enabling the longitudinal sections of the pseudo gate structures to be square, sequentially forming word line polycrystalline silicon and an insulating layer which are both in a sine wave shape on the dummy gate structure, and forming grid polycrystalline silicon on the insulating layer. The insulating layer is in a fluctuating sine wave shape, and the relative area between the word line polycrystalline silicon and the gate polycrystalline silicon is increased, so that the capacitance value of the PIP capacitor is increased. Moreover, the pseudo gate structure and the gate structure are formed at the same time, so that additional photomasks and process steps are not needed.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a PIP capacitor and a forming method. Background technique [0002] Up to now, semiconductor integrated circuit design has a variety of capacitors to choose from, including MOS (metal-oxide-semiconductor) capacitors, PIP (polysilicon-insulator-polysilicon) capacitors, MIM (metal-insulator-metal) capacitors, MOM ( metal-oxide-metal) capacitors, etc. In order to meet customers' requirements for capacitance characteristics and low cost, PIP capacitors have been widely used. [0003] Please refer to figure 1 , the prior art method for forming a PIP capacitor is to form a shallow trench isolation structure 120 in the substrate 110, and form a word line polysilicon 130 on the shallow trench isolation structure 120 as a lower-level plate of the PIP capacitor; on the word line polysilicon 130 The oxide layer 140 is formed as the insulating layer of the PIP capacitor; the gate p...

Claims

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Application Information

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IPC IPC(8): H01L49/02H01L27/108H01L21/8242
CPCH01L28/40H10B12/30H10B12/03H10B12/05H10B12/488
Inventor 汤志林王卉付永琴曹子贵
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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