OTP memory array and read-write method

Abstract

The invention discloses an OTP memory array and a read-write method, and relates to an integrated circuit technology. An OTP memory array is composed of M*N OTP memories, each OTP memory comprises a storage MOS transistor, a first MOS transistor, a second MOS transistor and a detection MOS transistor, and an isolation module is arranged between a control end of the detection MOS transistor and the storage MOS transistor; the storage MOS transistor is a Native MOS transistor, and both M and N are integers greater than 1; the isolation module is composed of at least one isolation MOS transistor, and the isolation MOS transistor is a Native MOS transistor. In the array, the grid electrodes of the storage MOS transistors are connected to a same storage control point, the isolation MOS transistors are distinguished according to the distance values from the MOS transistors, and the grid electrodes of the isolation MOS transistors with the same distance value are connected to a same isolation control point. According to the present invention, the leakage current can be greatly reduced, and the programming effect is improved.

Description

technical field [0001] The present invention relates to integrated circuit technology and OTP memory technology. Background technique [0002] Figure 1~Figure 4 4 prior art are shown, figure 1 For the XLPM memory cell prototype, figure 2 is an XLPM memory cell with a read isolation device, image 3 It is an XLPM memory cell with a high-voltage isolation device, Figure 4 It is an XLPM memory cell using NativeMOS gate capacitance. [0003] by figure 1 The XLPM memory cells shown are based on the figure 2 Adding the read isolation device M1 can isolate the crosstalk between the memory cells located on the common bit lines BL and BR. Moreover, due to the isolation function of this device, it is no longer necessary to perform the clearing operation of all cells, but only need to perform the clearing operation on the memory cells on the word line to be read, thereby reducing the power consumption caused thereby. [0004] image 3 A high-voltage isolation device with ...

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Problems solved by technology

[0008] figure 1 , figure 2 , image 3 There is a problem of Vt voltage drop loss caused by capacitor C0, MOS tube M3, MOS tube M4, etc.

[0009] figure 1 , figure 2 , image 3 , Figure 4 structure, the word line requires a larger area of ​​high-voltage decoding circuit, and the word line also requires a larger area of ​​3V medium voltage decoding circuit, while the word line has to handle high-low dual voltage switching, and the bit line has to handle medium-low Dual-voltage switching, the resulting design complexity of various voltage combinations, the risk of leakage caused by insufficient verification coverage, and numerous level-shifting interface circuits

[0010] also, figure 1 , figure 2 , image 3 , Figure 4 The peripheral circuit also has the problem of large Vt voltage drop loss and high read voltage due to the use of thick gate oxide devices (Vt is usually high, >0.7V) in the medium and high voltage paths.

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